公开(公告)号：US06772359B2

公开(公告)日：2004-08-03

申请号：US09725896

申请日：2000-11-30

申请人： Jong Tae Kwak ,  Dong Woo Shin ,  Jong Sup Baek ,  Choul Hee Koo ,  Nak Kyu Park

发明人： Jong Tae Kwak ,  Dong Woo Shin ,  Jong Sup Baek ,  Choul Hee Koo ,  Nak Kyu Park

IPC分类号： G06F104

CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G11C7/22 ,  G11C11/4076 ,  Y02D10/13 ,  Y02D10/14

摘要： A clock control circuit for a Rambus DRAM is provided which reduces power consumption by determining in advance whether an applied command is a read or current control command, and enabling a clock signal for externally outputting an internal data only during the read or current control command. Our circuit includes: an input signal detecting unit for generating an enable signal when one of a first comparing signal comparing an address value of the selected Rambus DRAM with a device address value of a COLC packet, and a second comparing signal comparing the address value of the selected Rambus DRAM with a device address value of a COLX packet is enabled, and when the command is a read or current control command; a signal generating unit for generating a clock enable signal for externally outputting an internal data when one of the first and second comparing signals is enabled; an output signal maintaining unit for outputting a control signal for maintaining the clock enable signal to the signal generating unit in the read or current control command; and an output signal control unit for outputting a control signal for controlling generation of the clock enable signal to the signal generating unit, when the command is not the read or current control command.

摘要翻译： 提供了一种用于Rambus DRAM的时钟控制电路，其通过预先确定所应用的命令是读取还是当前控制命令来降低功耗，并且仅在读取或当前控制命令期间启用用于外部输出内部数据的时钟信号。 我们的电路包括：输入信号检测单元，用于当将所选择的Rambus DRAM的地址值与COLC分组的设备地址值进行比较的第一比较信号中的一个产生使能信号，以及第二比较信号， 所选择的具有COLX分组的设备地址值的Rambus DRAM被使能，并且当命令是读取或当前控制命令时; 信号产生单元，用于当所述第一和第二比较信号之一被使能时，产生用于外部输出内部数据的时钟使能信号; 输出信号维持单元，用于在读取或当前控制命令中输出用于将时钟使能信号保持到信号生成单元的控制信号; 以及输出信号控制单元，用于当命令不是读取或当前控制命令时，向信号生成单元输出用于控制产生时钟使能信号的控制信号。

公开(公告)号：US06714605B2

公开(公告)日：2004-03-30

申请号：US10246365

申请日：2002-09-18

申请人： Gary L. Sugar ,  Karl A. Miller ,  Jong Sup Baek

发明人： Gary L. Sugar ,  Karl A. Miller ,  Jong Sup Baek

IPC分类号： H03D100

CPC分类号： H04W16/14 ,  G01R13/0254 ,  H04L1/1664 ,  H04W24/00 ,  H04W72/00

摘要： A spectrum analysis engine (SAGE) that comprises a spectrum analyzer component, a signal detector component, a universal signal synchronizer component and a snapshot buffer component. The spectrum analyzer component generates data representing a real-time spectrogram of a bandwidth of radio frequency (RF) spectrum. The signal detector detects signal pulses in the frequency band and outputs pulse event information entries output, which include the start time, duration, power, center frequency and bandwidth of each detected pulse. The signal detector also provides pulse trigger outputs which may be used to enable/disable the collection of information by the spectrum analyzer and the snapshot buffer components. The snapshot buffer collects a set of raw digital signal samples useful for signal classification and other purposes. The universal signal synchronizer synchronizes to periodic signal sources, useful for instituting schemes to avoid interference with those signals.

摘要翻译： 频谱分析引擎（SAGE），包括频谱分析仪组件，信号检测器组件，通用信号同步器组件和快照缓冲器组件。 频谱分析仪组件产生表示射频（RF）频谱带宽的实时谱图的数据。 信号检测器检测频带中的信号脉冲，并输出脉冲事件信息条目输出，其中包括每个检测脉冲的开始时间，持续时间，功率，中心频率和带宽。 信号检测器还提供脉冲触发输出，可用于启用/禁用频谱分析仪和快照缓冲器组件的信息采集。 快照缓冲器收集一组用于信号分类和其他目的的原始数字信号样本。 通用信号同步器与周期信号源同步，可用于建立避免干扰信号的方案。

公开(公告)号：US07224752B2

公开(公告)日：2007-05-29

申请号：US10757704

申请日：2004-01-14

申请人： Gary L. Sugar ,  Karl A. Miller ,  Jong Sup Baek

发明人： Gary L. Sugar ,  Karl A. Miller ,  Jong Sup Baek

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H04W16/14 ,  G01R13/0254 ,  H04L1/1664 ,  H04W24/00 ,  H04W72/00

摘要： A spectrum analysis engine (SAGE) that comprises a spectrum analyzer component, a signal detector component, a universal signal synchronizer component and a snapshot buffer component. The spectrum analyzer component generates data representing a real-time spectrogram of a bandwidth of radio frequency (RF) spectrum. The signal detector detects signal pulses in the frequency band and outputs pulse event information entries output, which include the start time, duration, power, center frequency and bandwidth of each detected pulse. The signal detector also provides pulse trigger outputs which may be used to enable/disable the collection of information by the spectrum analyzer and the snapshot buffer components. The snapshot buffer collects a set of raw digital signal samples useful for signal classification and other purposes. The universal signal synchronizer synchronizes to periodic signal sources, useful for instituting schemes to avoid interference with those signals.

摘要翻译： 频谱分析引擎（SAGE），包括频谱分析仪组件，信号检测器组件，通用信号同步器组件和快照缓冲器组件。 频谱分析仪组件产生表示射频（RF）频谱带宽的实时谱图的数据。 信号检测器检测频带中的信号脉冲，并输出脉冲事件信息条目输出，其中包括每个检测脉冲的开始时间，持续时间，功率，中心频率和带宽。 信号检测器还提供脉冲触发输出，可用于启用/禁用频谱分析仪和快照缓冲器组件的信息采集。 快照缓冲器收集一组用于信号分类和其他目的的原始数字信号样本。 通用信号同步器与周期信号源同步，可用于建立避免干扰信号的方案。

公开(公告)号：US07254191B2

公开(公告)日：2007-08-07

申请号：US10420511

申请日：2003-04-22

申请人： Gary L. Sugar ,  Karl A. Miller ,  Jong Sup Baek

发明人： Gary L. Sugar ,  Karl A. Miller ,  Jong Sup Baek

IPC分类号： H03D1/00 ,  H03L27/06

CPC分类号： H04W24/00 ,  H04L1/1664 ,  H04W16/14

摘要： A real-time spectrum analysis engine (SAGE) that comprises a spectrum analyzer component, a signal detector component, a universal signal synchronizer component and a snapshot buffer component. The spectrum analyzer component generates data representing a real-time spectrogram of a bandwidth of radio frequency (RF) spectrum. The signal detector detects signal pulses in the frequency band and outputs pulse event information entries output, which include the start time, duration, power, center frequency and bandwidth of each detected pulse. The signal detector also provides pulse trigger outputs which may be used to enable/disable the collection of information by the spectrum analyzer and the snapshot buffer components. The snapshot buffer collects a set of raw digital signal samples useful for signal classification and other purposes. The universal signal synchronizer synchronizes to periodic signal sources, useful for instituting schemes to avoid interference with those signals.

摘要翻译： 包括频谱分析仪组件，信号检测器组件，通用信号同步器组件和快照缓冲器组件的实时频谱分析引擎（SAGE）。 频谱分析仪组件产生表示射频（RF）频谱带宽的实时谱图的数据。 信号检测器检测频带中的信号脉冲，并输出脉冲事件信息条目输出，其中包括每个检测脉冲的开始时间，持续时间，功率，中心频率和带宽。 信号检测器还提供脉冲触发输出，可用于启用/禁用频谱分析仪和快照缓冲器组件的信息采集。 快照缓冲器收集一组用于信号分类和其他目的的原始数字信号样本。 通用信号同步器与周期信号源同步，可用于建立避免干扰信号的方案。

公开(公告)号：US6145113A

公开(公告)日：2000-11-07

申请号：US143346

申请日：1998-08-28

申请人： Jong Sup Baek

发明人： Jong Sup Baek

IPC分类号： G06F11/10 ,  H03M7/30 ,  H03M13/00 ,  H03M13/15 ,  H03M3/17

CPC分类号： H03M13/151

摘要： The present invention relates to a small size decoder reducing power consumption and more particularly to a series reed-Solomon decoder synchronized with a bit clock signal. In a Reed-Solomon decoder according to the present invention, the syndrome calculation part comprises a classification element for classifying the input coding data into an even data and an odd data and for calculating, in series, coefficient of the syndrome polynomial on bit-by-bit basis, being synchronized with a bit clock signal. The error position and estimation polynomial calculation part comprises a classification element for classifying an initial syndrome polynomial, a correction syndrome polynomial, an initial deletion pointer polynomial and an initial deletion pointer polynomial into an even data and an odd data and for an error value polynomial and an error position value polynomial on bit-by-bit basis, being synchronized with a bit clock signal. The error position polynomial root and error value calculation part comprises a substitution element for substituting roots for the error position polynomial and the error value polynomial, being synchronized with a bit clock signal, for accumulating results of the error position polynomial and the error value polynomial and for outputting error values for error correction, being synchronized with a byte clock signal.

摘要翻译： 本发明涉及一种减小功耗的小尺寸解码器，更具体地涉及与位时钟信号同步的串联专用Solomon解码器。 在根据本发明的里德 - 所罗门解码器中，校正子计算部分包括用于将输入的编码数据分类成偶数据和奇数数据的分类元素，并且用于逐位地计算校正子多项式的系数 与位时钟信号同步。 误差位置和估计多项式计算部分包括用于将初始校正子多项式，校正多项式，初始删除指针多项式和初始删除指针多项式分类为偶数据和奇数据以及用于错误值多项式的分类元素， 逐位的误差位置值多项式与位时钟信号同步。 误差位置多项式根和误差值计算部分包括用于将根代入误差位置多项式的替代元件和与位时钟信号同步的误差值多项式，用于累积误差位置多项式和误差值多项式的结果， 用于输出用于纠错的误差值，与字节时钟信号同步。