公开(公告)号：US08856410B2

公开(公告)日：2014-10-07

申请号：US13219637

申请日：2011-08-27

申请人： Nak Kyu Park

发明人： Nak Kyu Park

IPC分类号： G06F13/12 ,  G06F1/12 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C7/1012 ,  G11C7/222 ,  G11C2207/107 ,  G11C2207/2272

摘要： A semiconductor memory apparatus includes a synchronized signal generation circuit, a serial-to-parallel data conversion unit and a data storage region. The synchronized signal generation unit outputs one of a data input/output strobe signal and a delay locked clock signal as synchronized signals in response to a control signal in a write operation. The serial-to-parallel data conversion unit converts serial data into parallel data in response to the synchronized signals. The parallel data is stored in the data storage region.

摘要翻译： 半导体存储装置包括同步信号发生电路，串并转数据转换单元和数据存储区域。 同步信号生成单元响应于写入操作中的控制信号，将数据输入/输出选通信号和延迟锁定时钟信号中的一个作为同步信号输出。 串行到并行数据转换单元响应于同步信号将串行数据转换为并行数据。 并行数据存储在数据存储区域中。

公开(公告)号：US08854910B2

公开(公告)日：2014-10-07

申请号：US13450797

申请日：2012-04-19

申请人： Nak Kyu Park

发明人： Nak Kyu Park

IPC分类号： G11C7/00 ,  G11C11/406

CPC分类号： G11C11/40615 ,  G11C11/40622

摘要： A semiconductor memory device includes a memory core configured to sequentially activate first and second banks in response to first and second bank active signals which are sequentially enabled in response to first and second enable signals when a self-refresh operation is to be performed, select a word line by row addresses, and perform a refresh operation for memory cells which are connected with the word line; and an address counter configured to perform a counting operation for the row addresses in response to a counter signal, and interrupt the counting operation for the row addresses in a case where both the first and second banks are not activated when the self-refresh operation is ended.

摘要翻译： 半导体存储器件包括存储器核心，其被配置为响应于当要执行自刷新操作时响应于第一和第二使能信号被依次使能的第一和第二存储体活动信号来顺序地激活第一和第二存储体， 字行逐行地址，并对与字线连接的存储单元执行刷新操作; 以及地址计数器，被配置为响应于计数器信号对行地址执行计数操作，并且当自刷新操作是第二和第二存储体都不被激活时中断行地址的计数操作 结束了。

公开(公告)号：US08699285B2

公开(公告)日：2014-04-15

申请号：US13118674

申请日：2011-05-31

申请人： Nak Kyu Park

发明人： Nak Kyu Park

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084

摘要： A semiconductor memory device includes a write control signal generating circuit and a write enable signal generating unit. The write control signal generating circuit is configured to generate a write control signal activated during a time period from an input time point of a read command to an end time point of a data output time period. The write enable signal generating unit is configured to output a write command as a write enable signal in response to the write control signal.

摘要翻译： 半导体存储器件包括写入控制信号发生电路和写入使能信号产生单元。 写入控制信号发生电路被配置为产生在从读取命令的输入时间点到数据输出时间段的结束时间点的时间段期间被激活的写入控制信号。 写入使能信号生成单元被配置为响应于写入控制信号而将写入命令作为写入使能信号输出。

公开(公告)号：US08374042B2

公开(公告)日：2013-02-12

申请号：US13034937

申请日：2011-02-25

申请人： Nak Kyu Park

发明人： Nak Kyu Park

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1078 ,  G11C7/109 ,  G11C2207/2209

摘要： A command decoder includes a snoop read control signal generation unit that generates a snoop read control signal from a internal chip select signal according to a level of a transmission mode control signal, and an internal snoop read command generation unit that generates an internal snoop read command by driving a first node in response to an internal command and the snoop read control signal.

摘要翻译： 命令解码器包括：窥探读取控制信号生成单元，其根据发送模式控制信号的电平从内部片选信号生成窥探读控制信号;内窥读指令生成单元，生成内窥窥读指令 通过响应于内部命令和窥探读取控制信号来驱动第一节点。

公开(公告)号：US07995404B2

公开(公告)日：2011-08-09

申请号：US12347195

申请日：2008-12-31

申请人： Nak-Kyu Park

发明人： Nak-Kyu Park

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/222

摘要： A semiconductor IC device includes a core strobe signal generator configured to latch a read command signal according to an internal clock signal to generate a core strobe signal, a core block configured to output data stored in a memory cell in response to the core strobe signal, a data output unit configured to latch data output from the core block according to a plurality of control signals and output the latched data in a predetermined order, and a controller configured to generate the plurality of control signals by using both the core strobe signal and the internal clock signal.

摘要翻译： 一种半导体IC器件包括核心选通信号发生器，其被配置为根据内部时钟信号锁存读取命令信号以产生核心选通信号，核心块被配置为响应于核心选通信号输出存储在存储器单元中的数据， 数据输出单元，被配置为根据多个控制信号锁存从所述核心块输出的数据，并以预定顺序输出所述锁存数据;以及控制器，被配置为通过使用所述核心选通信号和所述控制信号来产生所述多个控制信号 内部时钟信号。

公开(公告)号：US07990174B2

公开(公告)日：2011-08-02

申请号：US12648359

申请日：2009-12-29

申请人： Nak Kyu Park

发明人： Nak Kyu Park

IPC分类号： H03K17/16

CPC分类号： G11C5/06 ,  H01L25/0657 ,  H01L2224/16

摘要： A circuit for calibrating impedance includes an enable signal generator, a code generator and a connection controller. The enable signal generator generates an enable signal in response to a chip selection signal. The code generator generates an impedance calibration code in response to the enable signal by using an external resistance coupled to an electrode. The connection controller controls connection between the code generator and the electrode in response to the enable signal.

摘要翻译： 用于校准阻抗的电路包括使能信号发生器，代码发生器和连接控制器。 使能信号发生器响应于芯片选择信号产生使能信号。 代码发生器通过使用耦合到电极的外部电阻来响应于使能信号产生阻抗校准码。 连接控制器响应于使能信号控制代码发生器和电极之间的连接。

公开(公告)号：US07696776B2

公开(公告)日：2010-04-13

申请号：US12026402

申请日：2008-02-05

申请人： Nak Kyu Park

发明人： Nak Kyu Park

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K3/00

CPC分类号： G11C11/406 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/4093

摘要： A circuit for generating an on-die termination control signal can include a first signal generation block configured to generate a first signal to prevent a first on-die terminal control from being performed in a frequency/voltage switching period, a second signal generation block configured to generate a second signal to perform a second on-die termination control at an initial stage of operation, and a signal output block configured to generate the on-die termination control signal by combining the first and second signals.

摘要翻译： 用于产生片上终端控制信号的电路可以包括：第一信号生成块，其被配置为生成第一信号，以防止在频率/电压切换周期中执行第一片上终端控制，第二信号生成块配置 以产生第二信号以在初始操作阶段执行第二片上终止控制;以及信号输出块，被配置为通过组合第一和第二信号来生成片上终止控制信号。

公开(公告)号：US20090180340A1

公开(公告)日：2009-07-16

申请号：US12345974

申请日：2008-12-30

申请人： Keun Soo Song ,  Nak Kyu Park

发明人： Keun Soo Song ,  Nak Kyu Park

IPC分类号： G11C29/00 ,  G11C17/16 ,  G11C8/00

CPC分类号： G11C29/785 ,  G11C2229/763

摘要： A semiconductor integrated circuit includes a semiconductor chip having an edge area and a bank area located an inner portion of the edge area, and a column redundancy fuse block disposed in the edge area.

摘要翻译： 半导体集成电路包括具有边缘区域和位于边缘区域的内部的堤区的半导体芯片，以及设置在边缘区域中的列冗余熔丝块。

公开(公告)号：US20070152728A1

公开(公告)日：2007-07-05

申请号：US11687068

申请日：2007-03-16

申请人： Nak Kyu Park

发明人： Nak Kyu Park

IPC分类号： G06F1/04

CPC分类号： H03K3/033 ,  H03K3/355

摘要： The disclosure is directed to an internal pulse generator outputting a signal with a constant pulse width nevertheless of a frequency of an input signal, including a first PMOS transistor, a PMOS second transistor and an NMOS transistor which are connected between a power supply voltage and a ground voltage in series, a latch and an inverter which are connected between an output terminal and a first node as a drain of the NMOS transistor, and a Y-time delay circuit connected between the output terminal and a second node that is a common gate of the PMOS and NMOS transistors.

摘要翻译： 本公开涉及内部脉冲发生器，其输出具有恒定脉冲宽度的信号，该信号具有输入信号的频率，包括第一PMOS晶体管，PMOS第二晶体管和NMOS晶体管，其连接在电源电压和 连接在输出端子和第一节点之间的串联接地电压，锁存器和反相器，作为NMOS晶体管的漏极，以及连接在输出端子和作为公共栅极的第二节点之间的Y延迟电路 的PMOS和NMOS晶体管。

公开(公告)号：US07205814B2

公开(公告)日：2007-04-17

申请号：US10878142

申请日：2004-06-28

申请人： Nak Kyu Park

发明人： Nak Kyu Park

IPC分类号： H03K3/00

CPC分类号： H03K3/033 ,  H03K3/355

摘要： The disclosure is directed to an internal pulse generator outputting a signal with a constant pulse width nevertheless of a frequency of an input signal, including a first PMOS transistor, a PMOS second transistor and an NMOS transistor which are connected between a power supply voltage and a ground voltage in series, a latch and an inverter which are connected between an output terminal and a first node as a drain of the NMOS transistor, and a Y-time delay circuit connected between the output terminal and a second node that is a common gate of the PMOS and NMOS transistors.

摘要翻译： 本公开涉及内部脉冲发生器，其输出具有恒定脉冲宽度的信号，该信号具有输入信号的频率，包括第一PMOS晶体管，PMOS第二晶体管和NMOS晶体管，其连接在电源电压和 连接在输出端子和第一节点之间的串联接地电压，锁存器和反相器，作为NMOS晶体管的漏极，以及连接在输出端子和作为公共栅极的第二节点之间的Y延迟电路 的PMOS和NMOS晶体管。