公开(公告)号：US20080099806A1

公开(公告)日：2008-05-01

申请号：US11872308

申请日：2007-10-15

Applicant: Jin Yeong KANG ,  Sang Heung LEE ,  Jin Gun KOO

Inventor： Jin Yeong KANG ,  Sang Heung LEE ,  Jin Gun KOO

IPC: H01L27/146 ,  H01L21/00

CPC classification number: H01L27/14689 ,  H01L27/14609 ,  H01L27/14681

Abstract: Provided are image sensor having a heterojunction bipolar transistor (HBT) and a method of fabricating the same. The image sensor is fabricated by use of silicon-germanium bipolar junction transistor complementary metal oxide semiconductor (SiGe BiCMOS) technology. In the image sensor, a PD employs a floating-base-type SiGe HBT unlike a pn-junction-based CMOS image sensor (CIS). A floating base of the SiGe HBT produces a positive (+) voltage with respect to a collector during an exposure process, and the HBT performs a reverse bipolar operation due to the positive voltage so that the collector and an emitter exchange functions. In particular, since the SiGe HBT obtains a current gain ten times as high as that of a typical bipolar device even during the reverse operation, the SiGe HBT cannot only sense an optical (image) current signal but also amplify the optical current signal. Thus, the image sensor requires only three transistors in a pixel so that the degree of integration can increase. Also, the floating base of the HBT is a SiGe or SiGeC epitaxial layer with a very small thickness of 150 Å or less, and even heavily doped B ions are barely thermally diffused due to the properties of the SiGe or SiGeC layer. As a result, the sensitivity of signals can improve in the short wavelength region, thus easily balancing three colors. Furthermore, since the image sensor is a direct signal current amplification type mechanism and senses an optical signal current in a steady mode, a sensing signal has excellent linearity, and thus both a sensing mechanism and control circuit are very simple.

Abstract translation: 提供了具有异质结双极晶体管（HBT）的图像传感器及其制造方法。 图像传感器通过使用硅 - 锗双极结型晶体管互补金属氧化物半导体（SiGe BiCMOS）技术制造。 在图像传感器中，PD采用基于pn结的CMOS图像传感器（CIS）的浮置型SiGe HBT。 SiGe HBT的浮动基极在曝光过程中产生相对于集电极的正（+）电压，并且HBT由于正电压而执行反向双极性操作，使得集电极和发射极交换功能起作用。 特别是，由于SiGe HBT即使在反向工作时也能获得比典型双极型器件高十倍的电流增益，所以SiGe HBT不仅可以检测光学（图像）电流信号，还可以放大光电流信号。 因此，图像传感器仅需要像素中的三个晶体管，使得集成度可以增加。 此外，HBT的浮动基底是具有150或更小厚度的非常小的SiGe或SiGeC外延层，并且由于SiGe或SiGeC层的性质，甚至重掺杂的B离子几乎没有热扩散。 结果，信号的灵敏度可以在短波长区域内改善，从而容易平衡三种颜色。 此外，由于图像传感器是直接信号电流放大型机构，并且在稳定模式下感测光信号电流，所以感测信号具有优异的线性度，因此感测机构和控制电路都非常简单。

公开(公告)号：US07141464B2

公开(公告)日：2006-11-28

申请号：US11179983

申请日：2005-07-12

Applicant: Jong Moon Park ,  Kun Sik Park ,  Seong Wook Yoo ,  Yong Sun Yoon ,  Sang Gi Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Bo Woo Kim

Inventor： Jong Moon Park ,  Kun Sik Park ,  Seong Wook Yoo ,  Yong Sun Yoon ,  Sang Gi Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Bo Woo Kim

IPC: H01L21/338

CPC classification number: H01L21/28587

Abstract: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible to readily perform a compound semiconductor device manufacturing process, and to reduce manufacturing cost by means of the increase of manufacturing yield and the simplification of manufacturing processes.

Abstract translation: 提供一种制造T型栅极的方法，包括以下步骤：分别在衬底上形成预定厚度的第一光致抗蚀剂层，阻挡层和第二光致抗蚀剂层; 在所述第二光致抗蚀剂层和所述阻挡层上形成T型栅极的主体图案; 暴露第二光致抗蚀剂层的预定部分以形成T型栅极的头部图案，并且进行热处理工艺以在除了T型的头部图案之外的第二光致抗蚀剂层的预定区域处产生交联 门; 在所得结构的整个表面上进行曝光处理，然后去除所述暴露部分; 在所得结构的整个表面上形成预定厚度的金属层，然后去除第一光致抗蚀剂层，阻挡层，产生交联的第二光致抗蚀剂层的预定区域和金属层 ，由此可以容易地进行化合物半导体器件制造工艺，并且通过增加制造成品率和简化制造工艺来降低制造成本。

公开(公告)号：US06852597B2

公开(公告)日：2005-02-08

申请号：US10071127

申请日：2002-02-08

Applicant: Il-Yong Park ,  Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Dae Woo Lee ,  Roh Tae Moon ,  Yang Yil Suk

Inventor： Il-Yong Park ,  Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Dae Woo Lee ,  Roh Tae Moon ,  Yang Yil Suk

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/7802

Abstract: A method for fabricating a power semiconductor device having a trench gate structure is provided. An epitaxial layer of a first conductivity type having a low concentration and a body region of a second conductivity type are sequentially formed on a semiconductor substrate of the first conductivity type having a high concentration. An oxide layer pattern is formed on the body region. A first trench is formed using the oxide layer pattern as an etching mask to perforate a predetermined portion of the body region having a first thickness. A body contact region of the second conductivity type having a high concentration is formed to surround the first trench by impurity ion implantation using the oxide layer pattern as an ion implantation mask. First spacer layers are formed to cover the sidewalls of the first trench and the sidewalls of the oxide layer pattern. A second trench is formed using the oxide layer pattern and the first spacer layers as etching masks to perforate a predetermined portion of the body region having a second thickness greater than the first thickness. A source region of the first conductivity type having a high concentration is formed to surround the second trench by impurity ion implantation using the oxide layer pattern and the first spacer layers as ion implantation masks. Second spacer layers are formed to cover the sidewalls of the second trench and the sidewalls of the first spacer layers. A third trench is formed to a predetermined depth of the epitaxial layer using the oxide layer pattern, the first spacer layers, and the second spacer layers as etching masks. A gate insulating layer is formed in the third trench. A gate conductive pattern is formed in the gate insulating layer. An oxide layer is formed on the gate conductive layer pattern. The first and second spacer layers are removed. A first metal electrode layer is formed to be electrically connected to the source region and the body contact region. A second metal electrode layer is formed to be electrically connected to the gate conductive layer pattern. A third metal electrode layer is formed to be electrically connected to the semiconductor substrate.

公开(公告)号：US06534365B2

公开(公告)日：2003-03-18

申请号：US09726910

申请日：2000-11-29

Applicant: Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Kee Soo Nam ,  Dae Woo Lee ,  Tae Moon Roh

Inventor： Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Kee Soo Nam ,  Dae Woo Lee ,  Tae Moon Roh

IPC: H01L21336

CPC classification number: H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

Abstract: A method of fabricating a vertical TDMOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.

Abstract translation: 使用侧壁间隔物和自对准技术制造垂直TDMOS功率器件的方法以及使用其的TDMOS功率器件。 TDMOS仅使用3个掩模制造，并且使用自对准技术形成源以体现高度集成的沟槽形成。 在此过程中，高浓度离子注入沟槽的底部使得厚的氧化膜在栅极的底部和拐角处生长，从而可以提高器件的电气特性，特别是漏电流和击穿电压。 此外，可以大大降低工艺步骤以降低工艺成本，可以实现高集成度，并且可以提高器件的可靠性。

公开(公告)号：US08629020B2

公开(公告)日：2014-01-14

申请号：US13228479

申请日：2011-09-09

Applicant: Sang Gi Kim ,  Jin-Gun Koo ,  Seong Wook Yoo ,  Jong-Moon Park ,  Jin Ho Lee ,  Kyoung Il Na ,  Yil Suk Yang ,  Jongdae Kim

Inventor： Sang Gi Kim ,  Jin-Gun Koo ,  Seong Wook Yoo ,  Jong-Moon Park ,  Jin Ho Lee ,  Kyoung Il Na ,  Yil Suk Yang ,  Jongdae Kim

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.

Abstract translation: 提供半导体器件及其制造方法。 该方法包括：在第一导电类型的半导体衬底中形成沟槽; 在所述沟槽的侧壁和底表面上形成包含第二导电类型的掺杂剂的沟槽掺杂剂层; 通过将所述沟槽掺杂剂含量层中的掺杂剂扩散到所述半导体衬底中来形成掺杂区域; 并去除含沟槽掺杂剂层。

公开(公告)号：US06774697B2

公开(公告)日：2004-08-10

申请号：US10325929

申请日：2002-12-23

Applicant: Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

Inventor： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

IPC: H03L500

CPC classification number: H03K19/0016

Abstract: The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit. The high voltage and the low voltage can be simultaneously driven using only a single output driving circuit and the single output driving circuit is constructed in multiple stages and is selectively driven by the output control register. Therefore, the power consumption can be saved.

Abstract translation: 本发明涉及输入和输出端口电路。 输入输出端口电路包括用于存储输出信号的信号寄存器，存储用于确定输入/输出方向的输入/输出控制信号的输入/输出寄存器，多个控制寄存器，用于 选择性地根据功率模式控制信号提供低电压或高电压;信号方向控制电路，用于根据信号寄存器的值确定信号的方向，以及输入/输出寄存器的值，输出控制 电路根据控制寄存器的值和信号方向控制电路的输出驱动，以及输出驱动电路，用于根据信号方向控制电路的输出输出低电压，高电压或接地值，以及 输出控制电路的输出。 高电压和低电压可以使用单个输出驱动电路同时驱动，单输出驱动电路构成多级，由输出控制寄存器有选择地驱动。 因此，可以节省功耗。

公开(公告)号：US06284605B1

公开(公告)日：2001-09-04

申请号：US09428403

申请日：1999-10-28

Applicant: Jong-Dae Kim ,  Sang-Gi Kim ,  Jin-Gun Koo ,  Dae-Yong Kim

Inventor： Jong-Dae Kim ,  Sang-Gi Kim ,  Jin-Gun Koo ,  Dae-Yong Kim

IPC: H01L21336

CPC classification number: H01L21/84 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203

Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.

Abstract translation: 一种制造半导体功率集成电路的方法包括以下步骤：形成具有至少一个有源区的半导体结构，其中有源区包括用于形成源的阱区和用于形成漏极区的漂移区，形成用于 有源区的隔离，其中沟槽具有来自半导体结构的表面的预定深度，在沟槽内部和半导体结构之上形成第一TEOS氧化物层，其中第一TEOS氧化物层具有来自该半导体结构的预定厚度 在所述第一TEOS氧化物层上形成第二TEOS氧化物层，其中所述第二TEOS氧化物层的厚度小于所述第一TEOS氧化物层的厚度，并且对所述第一TEOS氧化物层进行选择性蚀刻 第一和第二TEOS氧化物层，从而同时形成场氧化物层图案，二极管绝缘层图案和栅极氧化物层图案 y减少加工步骤并获得低导通电阻。

公开(公告)号：US6087232A

公开(公告)日：2000-07-11

申请号：US135645

申请日：1998-08-18

Applicant: Jong Dae Kim ,  Sang Ki Kim ,  Jin Gun Koo ,  Kee Soo Nam

Inventor： Jong Dae Kim ,  Sang Ki Kim ,  Jin Gun Koo ,  Kee Soo Nam

IPC: H01L21/02 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L29/7835

Abstract: According to a method for manufacturing double RESURF (reduced SURface Field) LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors, on-resistance of double RESURF LDMOS transistors has been improved by using a new tapered p top layer on the surface of the drift region of the transistor, thereby decreasing the length of the drift region. Another advantage of the current invention is that the breakdown voltage similar with the on-resistance can be improved by using a reproducible tapered TEOS oxide by use of a multi-layer structure and low temperature annealing process. This is due to the reducing of the current path and impurity segregation in the drift region by using the tapered TEOS oxide instead of LOCOS filed oxide.

Abstract translation: 根据制造双RESURF（减少的SURface Field）LDMOS（侧向扩散金属氧化物半导体）晶体管的方法，通过在漂移区的表面上使用新的锥形p顶层，改善了双RESURF LDMOS晶体管的导通电阻 晶体管，从而减小漂移区的长度。 本发明的另一个优点是可以通过使用多层结构和低温退火工艺使用可再现的锥形TEOS氧化物来改善与导通电阻相似的击穿电压。 这是由于通过使用锥形TEOS氧化物而不是LOCOS氧化物来减少漂移区中的电流路径和杂质偏析。

公开(公告)号：US07741665B2

公开(公告)日：2010-06-22

申请号：US11872922

申请日：2007-10-16

Applicant: Jin Yeong Kang ,  Jin Gun Koo ,  Sang Heung Lee

Inventor： Jin Yeong Kang ,  Jin Gun Koo ,  Sang Heung Lee

IPC: H01L31/062 ,  H01L31/113

CPC classification number: H01L27/14689 ,  H01L27/14609

Abstract: Provided are a high-quality CMOS image sensor and a photo diode, which can be fabricated in sub-90 nm regime using nanoscale CMOS technology. The photo diode includes: a p-type well; an internal n-type region formed under a surface of the p-type well; and a surface p-type region including a highly doped p-type SiGeC epitaxial layer or a polysilicon layer deposited on a top surface of the p-type well over the internal n-type region. The image sensor includes: a photo diode including an internal n-type region and a surface p-type region; a transfer transistor for transmitting photo-charges generated in the photo diode to a floating diffusion node; and a driving transistor for amplifying a variation in an electric potential of the floating diffusion node due to the photo-charges. The image sensor further includes a floating metal layer for functioning as the floating diffusion node and applying an electric potential from a drain of the transfer transistor to a gate of the driving transistor.

Abstract translation: 提供了一种高质量CMOS图像传感器和光电二极管，其可以使用纳米级CMOS技术在亚90nm范围内制造。 光电二极管包括：p型阱; 形成在p型阱的表面下的内部n型区域; 以及表面p型区域，其包括在内部n型区域上沉积在p型阱的顶表面上的高掺杂p型SiGeC外延层或多晶硅层。 图像传感器包括：包含内部n型区域和表面p型区域的光电二极管; 用于将在光电二极管中产生的光电荷传输到浮动扩散节点的传输晶体管; 以及用于放大由于光电荷引起的浮动扩散节点的电位变化的驱动晶体管。 图像传感器还包括浮动金属层，用作浮动扩散节点并将电势从传输晶体管的漏极施加到驱动晶体管的栅极。

公开(公告)号：US07190432B2

公开(公告)日：2007-03-13

申请号：US11249783

申请日：2005-10-13

Applicant: Sang Gi Kim ,  Ju Wook Lee ,  Jong Moon Park ,  Seong Wook Yoo ,  Kun Sik Park ,  Yong Sun Yoon ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Boo Woo Kim

Inventor： Sang Gi Kim ,  Ju Wook Lee ,  Jong Moon Park ,  Seong Wook Yoo ,  Kun Sik Park ,  Yong Sun Yoon ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Boo Woo Kim

IPC: G03B27/32 ,  G03B27/42 ,  G03B27/70 ,  G03B27/54

CPC classification number: G03F7/70425

Abstract: Provided is a wafer exposure apparatus used in a semiconductor device manufacturing process, the exposure apparatus including: a reflective mirror for reflecting light provided from a light source; an optical path changer for changing a path of the light provided from the reflective mirror; first mirrors installed at both sides of the optical path changer to change the path of the light; second mirrors installed at both sides of a material to change the path of the light; and third mirrors installed at both sides of a mask to enter the light reflected by the first mirrors to the mask and to enter the light passed through the mask into the second mirrors, whereby it is possible to continuously expose one surface, both surfaces or a specific surface of a wafer in a state that the wafer is once aligned.

Abstract translation: 提供了一种在半导体器件制造工艺中使用的晶片曝光装置，该曝光装置包括：用于反射从光源提供的光的反射镜; 用于改变从反射镜提供的光的路径的光路改变器; 首先将镜子安装在光路改换器的两侧，以改变光线的路径; 第二个镜子安装在材料的两侧以改变光线的路径; 和第三反射镜，其安装在掩模的两侧，以将由第一反射镜反射的光进入掩模，并将通过掩模的光进入第二反射镜，由此可以连续地将一个表面，两个表面或一个 在晶片一次对准的状态下晶片的比表面。