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    Semiconductor device with input and/or output protective circuit
    3.
    发明授权
    Semiconductor device with input and/or output protective circuit 失效
    具有输入和/或输出保护电路的半导体器件

    公开(公告)号：US4733285A

    公开(公告)日：1988-03-22

    申请号：US758353

    申请日：1985-07-24

    申请人： Hiroshi Ishioka ,  Tohru Tsujide ,  Makoto Miyazawa

    发明人： Hiroshi Ishioka ,  Tohru Tsujide ,  Makoto Miyazawa

    IPC分类号： H01L27/08 ,  H01L27/02 ,  H01L29/78 ,  H01L29/04

    CPC分类号： H01L27/0251

    摘要： An MOSIC is provided with an input and/or output protective circuit which includes a first semiconductor region formed in a semiconductor substrate with a PN junction and electrically coupled between an input or output terminal and a transistor to be protected and a second semiconductor region formed so as to surround the first region. The PN junction formed between the second region and the substrate is reverse-biased, whereby the second region absorbs carriers which are undesirably injected from the first region into the substrate in an electrical operation of the IC.

    摘要翻译： MOSIC提供有输入和/或输出保护电路，其包括形成在具有PN结的半导体衬底中并电耦合在输入或输出端子和被保护晶体管之间的第一半导体区域和形成为第二半导体区域的第二半导体区域 围绕第一区域。 形成在第二区域和衬底之间的PN结被反向偏置，由此在IC的电气操作中，第二区域吸收不期望地从第一区域注入到衬底中的载流子。

    Switching circuit
    5.
    发明授权
    Switching circuit 有权
    开关电路

    公开(公告)号：US08760223B2

    公开(公告)日：2014-06-24

    申请号：US13490101

    申请日：2012-06-06

    申请人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Hiroshi Ishioka

    发明人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka

    IPC分类号： H02M3/07

    CPC分类号： H03K17/04123 ,  H03K2217/0036 ,  H03K2217/0045 ,  H03K2217/009

    摘要： A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

    摘要翻译： 根据一个实施例的开关电路是包括具有输入，输出和公共端子的至少一个半导体开关元件的开关电路，脉冲状信号被施加在输入端和公共端子之间以切换输出和 公共终端 开关电路还包括电容抑制元件部分，其连接在输入和输出端子之间，输入端子公共端子之间以及输出端子和公共端子之间的至少一个。 电容抑制元件部分减小了电容抑制元件部分连接的半导体开关元件的端子之间的寄生电容小于当电容抑制元件部分未以N倍的频率连接时获得的寄生电容（N为 1或更高）与脉冲状信号的时钟频率一样高。

    SWITCHING CIRCUIT
    6.
    发明申请
    SWITCHING CIRCUIT 有权
    切换电路

    公开(公告)号：US20120306288A1

    公开(公告)日：2012-12-06

    申请号：US13490240

    申请日：2012-06-06

    申请人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka ,  Hiroshi Ishioka

    发明人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka ,  Hiroshi Ishioka

    IPC分类号： H01H47/00

    CPC分类号： H03K17/04123 ,  H03K2217/0036 ,  H03K2217/0045 ,  Y10T307/747

    摘要： A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

    摘要翻译： 根据一个实施例的开关电路包括第一至第四半导体开关元件。 脉冲状信号被施加到开关元件的每个输入端子，使得当第一和第四开关元件处于导通（OFF）状态时，剩余的开关元件处于断开（ON）状态。 开关电路包括第一和第二电容元件。 连接在第二半导体开关元件的输出端子和连接在第二半导体开关元件的输入端子和第四半导体开关元件的输出端子之间的第二电容元件之间的第一电容元件具有电容以减小第二半导体开关元件的输出端之间的寄生电容 以与脉冲状信号的时钟频率相同的频率N倍（N为1以上的整数）的第四开关元件和第二开关元件的输入输出端子。

    Synchronous DRAM having a high data transfer rate
    7.
    发明授权
    Synchronous DRAM having a high data transfer rate 有权
    具有高数据传输速率的同步DRAM

    公开(公告)号：US5953286A

    公开(公告)日：1999-09-14

    申请号：US139571

    申请日：1998-08-25

    申请人： Yasushi Matsubara ,  Hiroshi Ishioka

    发明人： Yasushi Matsubara ,  Hiroshi Ishioka

    IPC分类号： G11C11/407 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C8/00

    CPC分类号： G11C7/1072 ,  G11C7/22

    摘要： In a semiconductor memory including a plurality of synchronous DRAMs controlled by one common memory controller, each of the synchronous DRAMs has first and second terminals for receiving a reference clock supplied from the memory controller. A signal line for this reference clock is laid out in such a manner that the signal line is connected from the memory controller firstly to the first terminal of the most remote synchronous DRAM, and then, to respective first terminals of the remaining synchronous DRAMs, in order, towards the nearest synchronous DRAM and further, to the second terminal of the nearest synchronous DRAM, and then, to respective second terminals of the remaining synchronous DRAMs, in order, towards the most remote synchronous DRAM. Thus, on the basis of the difference in phase between the same reference clock applied to the first and second terminals, each of synchronous DRAMs can obtain a delay information of the same synchronous DRAM attributable to the location of the same synchronous DRAM from the memory controller, and therefore, can set an optimum read-out data outputting timing, so that the setup time and the hold time for the read-out data supplied from all the synchronous DRAMs can be ensured. Thus, the reading operation can be speeded up by elevating the clock frequency.

    摘要翻译： 在包括由一个公共存储器控制器控制的多个同步DRAM的半导体存储器中，每个同步DRAM具有用于接收从存储器控制器提供的参考时钟的第一和第二端子。 用于该参考时钟的信号线布置成使得信号线从存储器控制器首先连接到最远端同步DRAM的第一端，然后连接到剩余的同步DRAM的相应的第一端， 朝向最近的同步DRAM，并且进一步到达最近的同步DRAM的第二终端，然后依次向剩余的同步DRAM的相应的第二终端发送到最远的同步DRAM。 因此，基于施加到第一和第二端子的相同参考时钟之间的相位差，每个同步DRAM可以从存储器控制器获得归因于相同同步DRAM的位置的相同同步DRAM的延迟信息 因此能够设定最佳的读出数据输出定时，从而可以确保从所有同步DRAM提供的读出数据的建立时间和保持时间。 因此，可以通过升高时钟频率来加快读取操作。

    Switching circuit
    9.
    发明授权
    Switching circuit 有权
    开关电路

    公开(公告)号：US08766699B2

    公开(公告)日：2014-07-01

    申请号：US13490240

    申请日：2012-06-06

    申请人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Hiroshi Ishioka

    发明人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka

    IPC分类号： H03K17/30

    CPC分类号： H03K17/04123 ,  H03K2217/0036 ,  H03K2217/0045 ,  Y10T307/747

    摘要： A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

    摘要翻译： 根据一个实施例的开关电路包括第一至第四半导体开关元件。 脉冲状信号被施加到开关元件的每个输入端子，使得当第一和第四开关元件处于导通（OFF）状态时，剩余的开关元件处于断开（ON）状态。 开关电路包括第一和第二电容元件。 连接在第二半导体开关元件的输出端子和连接在第二半导体开关元件的输入端子和第四半导体开关元件的输出端子之间的第二电容元件之间的第一电容元件具有电容以减小第二半导体开关元件的输出端之间的寄生电容 以与脉冲状信号的时钟频率相同的频率N倍（N为1以上的整数）的第四开关元件和第二开关元件的输入输出端子。

    SWITCHING CIRCUIT
    10.
    发明申请
    SWITCHING CIRCUIT 有权
    切换电路

    公开(公告)号：US20120306563A1

    公开(公告)日：2012-12-06

    申请号：US13490101

    申请日：2012-06-06

    申请人： Kazuhiro FUJIKAWA ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka ,  Hiroshi Ishioka

    发明人： Kazuhiro FUJIKAWA ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka ,  Hiroshi Ishioka

    IPC分类号： H03K17/687

    CPC分类号： H03K17/04123 ,  H03K2217/0036 ,  H03K2217/0045 ,  H03K2217/009

    摘要： A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

    摘要翻译： 根据一个实施例的开关电路是包括具有输入，输出和公共端子的至少一个半导体开关元件的开关电路，脉冲状信号被施加在输入端和公共端子之间以切换输出和 公共终端 开关电路还包括电容抑制元件部分，其连接在输入和输出端子之间，输入端子公共端子之间以及输出端子和公共端子之间的至少一个。 电容抑制元件部分减小了电容抑制元件部分连接的半导体开关元件的端子之间的寄生电容小于当电容抑制元件部分未以N倍的频率连接时获得的寄生电容（N为 1或更高）与脉冲状信号的时钟频率一样高。