公开(公告)号：US07535087B2

公开(公告)日：2009-05-19

申请号：US11692563

申请日：2007-03-28

Applicant: Hideyuki Inotsume ,  Hirokazu Fukuda

Inventor： Hideyuki Inotsume ,  Hirokazu Fukuda

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L23/49537 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: By disposing a rear surface of a first island 12 and a top surface of a second island 13 so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip 20 are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

Abstract translation: 通过将第一岛12的后表面和第二岛13的顶表面设置为至少部分地彼此重叠，第一岛上的第一半导体芯片和第二岛的后表面上的第二半导体芯片 被配置为彼此重叠。 因此，平面占用面积可以设定为小于两个芯片的平面面积。 此外，要连接到第二半导体芯片20的细金属线延伸到背面。 因此，也可以减小半导体器件的厚度。

公开(公告)号：US06833616B2

公开(公告)日：2004-12-21

申请号：US10310139

申请日：2002-12-05

Applicant: Tetsuro Asano ,  Mikito Sakakibara ,  Hideyuki Inotsume ,  Haruhiko Sakai ,  Shigeo Kimura

Inventor： Tetsuro Asano ,  Mikito Sakakibara ,  Hideyuki Inotsume ,  Haruhiko Sakai ,  Shigeo Kimura

IPC: H05K111

CPC classification number: H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0605 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor chip is mounted on a wiring board that has a two-layer lead structure. One of the leads used for receiving input signals is disposed on the lower layer and runs underneath the semiconductor chip forming an U-shaped wiring line while other leads are disposed on the upper layer. Because one of the upper layer leads for receiving input signals is disposed in the U-shaped pocket of the U-shaped wiring line of the lower layer, the relative positioning of corresponding terminals can be changed into a reversal of the positioning of the electrode pads of the chip connected to the terminals. Furthermore, one of the upper layer lead for receiving control signals is placed between the chip and the lower layer lead underneath the chip to prevent high frequency signal interference.

Abstract translation: 半导体芯片安装在具有双层引线结构的布线板上。 用于接收输入信号的引线之一被布置在下层上并且在形成U形布线的半导体芯片的下方延伸，而在上层设置其它引线。 由于用于接收输入信号的上层引线之一设置在下层的U形布线的U形槽中，所以相应端子的相对定位可以改变为电极焊盘的定位的反转 的芯片连接到终端。 此外，用于接收控制信号的上层引线之一被放置在芯片和芯片下方的下层引线之间，以防止高频信号干扰。

公开(公告)号：US06818969B2

公开(公告)日：2004-11-16

申请号：US10283365

申请日：2002-10-30

Applicant: Tetsuro Asano ,  Mikito Sakakibara ,  Hideyuki Inotsume ,  Haruhiko Sakai ,  Shigeo Kimura

Inventor： Tetsuro Asano ,  Mikito Sakakibara ,  Hideyuki Inotsume ,  Haruhiko Sakai ,  Shigeo Kimura

IPC: H01L23495

CPC classification number: H01L23/49838 ,  H01L21/4832 ,  H01L23/4824 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49844 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0605 ,  H01L2223/6644 ,  H01L2223/6688 ,  H01L2224/05554 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H03K17/002 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device includes four input terminals, four leads extending from the corresponding input terminals and a semiconductor chip that has a first circuit and a second circuit and is mounted on one of the leads. The lead having the semiconductor chip thereon bends in a plane of the substrate so that an end portion and a mid portion of the lead are exposed on one side of the semiconductor chip. One of the input electrode pads of the first circuit is connected to the end portion of the lead by a bonding wire. The end portion of the lead is on the opposite side of the mid portion of the lead with respect to one of the leads that is connected to one of the input electrode pads of the second circuit by a bonding wire. This configuration achieves a crossing wiring structure within the packaging. By changing the connection of bonding wires, the crossing wiring structure is easily undone.

Abstract translation: 半导体器件包括四个输入端子，从相应的输入端子延伸的四个引线和具有第一电路和第二电路并且安装在引线之一上的半导体芯片。 其上具有半导体芯片的引线在基板的平面中弯曲，使得引线的端部和中间部分在半导体芯片的一侧露出。 第一电路的输入电极焊盘之一通过接合线连接到引线的端部。 引线的端部相对于通过接合线连接到第二电路的一个输入电极焊盘的引线之一位于引线的中间部分的相对侧。 该配置实现了包装内的交叉布线结构。 通过改变接合线的连接，交叉布线结构容易被取消。

公开(公告)号：US07554183B2

公开(公告)日：2009-06-30

申请号：US11861697

申请日：2007-09-26

Applicant: Hideyuki Inotsume ,  Hirokazu Fukuda

Inventor： Hideyuki Inotsume ,  Hirokazu Fukuda

IPC: H01L23/02

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

Abstract translation: 具有安装在引线框架上的多个半导体芯片的半导体器件通过减小其平面尺寸和厚度而被小型化。 通过将第一岛的后表面和第二岛的顶表面设置为至少部分地彼此重叠，在第一岛上的第一半导体芯片和第二岛的后表面上的第二半导体芯片被配置 以便彼此重叠。 因此，平面占用面积可以设定为小于两个芯片的平面面积。 此外，要连接到第二半导体芯片的细金属线延伸到背面。 因此，也可以减小半导体器件的厚度。

公开(公告)号：US20070228537A1

公开(公告)日：2007-10-04

申请号：US11692563

申请日：2007-03-28

Applicant: Hideyuki Inotsume ,  Hirokazu Fukuda

Inventor： Hideyuki Inotsume ,  Hirokazu Fukuda

IPC: H01L23/02

CPC classification number: H01L23/49537 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: By disposing a rear surface of a first island 12 and a top surface of a second island 13 so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip 20 are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

Abstract translation: 通过将第一岛12的后表面和第二岛13的顶表面设置成至少部分地彼此重叠，第一岛上的第一半导体芯片和第二岛的后表面上的第二半导体芯片 被配置为彼此重叠。 因此，平面占用面积可以设定为小于两个芯片的平面面积。 此外，要连接到第二半导体芯片20的细金属线延伸到背面。 因此，也可以减小半导体器件的厚度。

公开(公告)号：US20080203582A1

公开(公告)日：2008-08-28

申请号：US11861697

申请日：2007-09-26

Applicant: Hideyuki Inotsume ,  Hirokazu Fukuda

Inventor： Hideyuki Inotsume ,  Hirokazu Fukuda

IPC: H01L23/52

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

Abstract translation: 具有安装在引线框架上的多个半导体芯片的半导体器件通过减小其平面尺寸和厚度而被小型化。 通过将第一岛的后表面和第二岛的顶表面设置为至少部分地彼此重叠，在第一岛上的第一半导体芯片和第二岛的后表面上的第二半导体芯片被配置 以便彼此重叠。 因此，平面占用面积可以设定为小于两个芯片的平面面积。 此外，要连接到第二半导体芯片的细金属线延伸到背面。 因此，也可以减小半导体器件的厚度。

公开(公告)号：US06833608B2

公开(公告)日：2004-12-21

申请号：US10294912

申请日：2002-11-15

Applicant: Tetsuro Asano ,  Mikito Sakakibara ,  Hideyuki Inotsume ,  Haruhiko Sakai ,  Shigeo Kimura

Inventor： Tetsuro Asano ,  Mikito Sakakibara ,  Hideyuki Inotsume ,  Haruhiko Sakai ,  Shigeo Kimura

IPC: H01L23495

CPC classification number: H01L24/32 ,  H01L23/49562 ,  H01L23/49844 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L27/0605 ,  H01L2224/05554 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01032 ,  H01L2224/45099

Abstract: Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern. Two of the leads of the lead pattern provides space enough for wire-bonding connection to corresponding electrode pads on the semiconductor chip at both ends of the semiconductor chip. Because each of electrode pads can be connected to the corresponding lead at either end of the semiconductor chip, two sets of bonding wire connection between the leads and the electrode pads provides two different switches with two different signal inputs scheme.

Abstract translation: 通过将相同的半导体芯片安装在相同的引线图案上来制造具有两个不同信号输入方案的两个不同的开关。 引线图案的两个引线提供足够的空间，用于与半导体芯片两端的半导体芯片上的相应电极焊盘的引线接合连接。 因为每个电极焊盘可以连接到半导体芯片的任一端处的对应引线，所以引线和电极焊盘之间的两组接合线连接提供具有两种不同信号输入方案的两个不同的开关。