公开(公告)号：US20100033647A1

公开(公告)日：2010-02-11

申请号：US12462525

申请日：2009-08-05

Applicant: Yoshitaka Okita ,  Hidekazu Takata ,  Masato Imanishi ,  Kazuya Fujita

Inventor： Yoshitaka Okita ,  Hidekazu Takata ,  Masato Imanishi ,  Kazuya Fujita

IPC: G02F1/1335 ,  G02F1/13 ,  G02B6/06

CPC classification number: H04N5/2253 ,  G02F1/133526 ,  H01L27/14601 ,  H01L27/14625

Abstract: A display element and electronic element module according to the present invention is described, in which a lens is formed as part of a translucent support substrate having a display disposed thereon, the lens being formed on a part other than where the display is disposed, where an electronic element is disposed for the lens.

Abstract translation: 描述了根据本发明的显示元件和电子元件模块，其中透镜被形成为具有设置在其上的显示器的半透明支撑基板的一部分，透镜形成在除了显示器设置的部分之外的部分上，其中 为透镜设置电子元件。

公开(公告)号：US06262910B1

公开(公告)日：2001-07-17

申请号：US09417274

申请日：1999-10-13

Applicant: Hidekazu Takata ,  Kengo Maeda

Inventor： Hidekazu Takata ,  Kengo Maeda

IPC: G11C1112

CPC classification number: G11C11/22

Abstract: A switching transistor is provided which applies predetermined voltage to a plurality of word lines based on a predetermined signal from a power on reset circuit, until predetermined potential becomes stable, when the predetermined potential is applied to the bit line or to the plate line, such as at the time of power on, to connect the bit line connected to each memory cell and the memory cell capacitor, as well as applies a control signal to the gate to thereby electrically connect the bit line and the plate line.

Abstract translation: 提供了一种开关晶体管，当预定电位施加到位线或板线时，基于来自上电复位电路的预定信号，将预定电压施加到多个字线，直到预定电位变稳定为止 在上电时，连接连接到每个存储单元的位线和存储单元电容器，以及向门施加控制信号从而电连接位线和板线。

公开(公告)号：US6038162A

公开(公告)日：2000-03-14

申请号：US256941

申请日：1999-02-24

Applicant: Hidekazu Takata ,  Hidehiko Tanaka

Inventor： Hidekazu Takata ,  Hidehiko Tanaka

IPC: G11C14/00 ,  G11C11/22

CPC classification number: G11C11/22

Abstract: A semiconductor memory device includes: a plurality of word lines; a plurality of drive lines; a word line driving section for activating one of the plurality of word lines in accordance with a row address; a column selection section for, in accordance with a column address, selecting one of a plurality of ferroelectric memory cells coupled to the activated word line; a plate driving signal application section for applying a plate driving signal to at least a selected one of the plurality of drive lines, the at least one selected drive line being associated with the activated word line; and a switching section for coupling or detaching the plurality of ferroelectric memory cells to or from the at least one selected drive line. The column selection section controls the switching section so that only the selected ferroelectric memory cell is coupled to the at least one selected drive line.

Abstract translation: 半导体存储器件包括：多个字线; 多个驱动线; 字线驱动部，用于根据行地址来激活所述多个字线中的一个; 列选择部分，用于根据列地址选择耦合到激活字线的多个铁电存储器单元中的一个; 板驱动信号施加部，用于将板驱动信号施加到所述多个驱动线中的至少一个选择的驱动线，所述至少一个所选驱动线与所述激活字线相关联; 以及切换部分，用于将所述多个铁电存储器单元耦合到所述至少一个所选驱动线路或从所述至少一个所选择的驱动线路分离。 列选择部分控制切换部分，使得仅选择的铁电存储器单元耦合到至少一个所选择的驱动线。

公开(公告)号：US5828596A

公开(公告)日：1998-10-27

申请号：US723949

申请日：1996-09-26

Applicant: Hidekazu Takata ,  Thomas Mnich ,  David Novosel

Inventor： Hidekazu Takata ,  Thomas Mnich ,  David Novosel

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/407

CPC classification number: G11C11/22

Abstract: A semiconductor memory device includes a ferroelectric memory having a non-volatile operation mode and a volatile operation mode; an input terminal to which an input signal indicating a voltage level of a power source voltage is input; a first signal generating circuit outputting a first control signal for regulating activation and inactivation of the non-volatile operation mode to the ferroelectric memory; and a second signal generating circuit outputting a second control signal for regulating the activation and inactivation of the non-volatile operation mode to the first signal generating circuit, based on the input signal. The non-volatile operation mode and the volatile operation mode are automatically switched with each other in accordance with changes in the voltage level of the power source voltage under a first operation condition, and only the volatile operation mode is activated under a second operation condition.

Abstract translation: 半导体存储器件包括具有非易失性操作模式和易失性操作模式的铁电存储器; 输入表示电源电压的电压电平的输入信号的输入端子; 第一信号发生电路，输出用于调节非易失性操作模式的激活和失活的第一控制信号到铁电存储器; 以及第二信号发生电路，基于输入信号，输出用于调节对第一信号发生电路的非易失性操作模式的激活和失活的第二控制信号。 根据第一操作条件下的电源电压的电压电平的变化，非挥发性操作模式和易失性操作模式彼此自动切换，并且在第二操作条件下仅激活易失性操作模式。

公开(公告)号：US5457671A

公开(公告)日：1995-10-10

申请号：US338892

申请日：1994-11-14

Applicant: Hidekazu Takata ,  Shigenori Yanagi

Inventor： Hidekazu Takata ,  Shigenori Yanagi

IPC: G11B7/085

CPC classification number: G11B7/08541 ,  G11B7/08505

Abstract: In order to correct a track zero-crossing signal TZC generated from a signal detected by an optical head of an optical disk system, an expected edge pulse and a window signal are generated at the position at which the appearance of the edge of the track zero-crossing signal is expected. Among the edge pulses of the actual track zero-crossing signal, only those that exist inside a window are allowed to pass through. When the edge pulses do not exist within the window, the expected pulse is inserted so as to generate a corrected edge pulse, and a corrected track zero-crossing signal is generated from this corrected edge pulse.

Abstract translation: 为了校正由光盘系统的光头检测到的信号产生的轨道过零信号TZC，在轨道零点的边缘出现的位置处产生预期的边缘脉冲和窗口信号 交叉信号是预期的。 在实际轨道过零信号的边缘脉冲之中，只允许存在于窗口内的信号通过。 当窗口内不存在边缘脉冲时，插入预期脉冲以产生校正的边沿脉冲，并且从该校正的边沿脉冲产生校正的磁道过零信号。

公开(公告)号：US06751716B2

公开(公告)日：2004-06-15

申请号：US09834519

申请日：2001-04-12

Applicant: Ken Sumitani ,  Hidekazu Takata ,  Yuji Tanaka ,  Yasuyuki Aikawa

Inventor： Ken Sumitani ,  Hidekazu Takata ,  Yuji Tanaka ,  Yasuyuki Aikawa

IPC: G06F1200

CPC classification number: G06F21/79 ,  G06F12/1441 ,  G06F12/1466 ,  G11C8/20 ,  G11C16/22

Abstract: A semiconductor storage device including: a memory having a memory space, a plurality of addresses of the memory space each having data stored therein; and a security circuit for controlling a security function which activates or deactivates at least a part of the memory space according to whether, in the case where an address input to the security-circuit matches at least one key-address included in the security circuit, data stored in the address in the memory space is manipulated under a condition equal to a predetermined condition or under a condition not equal to the predetermined condition.

Abstract translation: 一种半导体存储装置，包括：具有存储器空间的存储器，存储有数据的存储器空间的多个地址; 以及用于控制安全功能的安全电路，其根据在安全电路输入的地址与包括在安全电路中的至少一个密钥地址匹配的情况下，激活或去激活存储器空间的至少一部分， 存储在存储器空间中的地址中的数据在等于预定条件的条件下或在不等于预定条件的条件下被操纵。

公开(公告)号：US06185146B2

公开(公告)日：2001-02-06

申请号：US09056282

申请日：1998-04-07

Applicant: Kazutomo Shioyama ,  Hidekazu Takata

Inventor： Kazutomo Shioyama ,  Hidekazu Takata

IPC: G11C800

CPC classification number: G11C8/12

Abstract: A semiconductor memory device includes a plurality of memory arrays including a plurality of memory cells; a plurality of fuses having one of a disconnected state and a connected state for classifying the plurality of memory arrays into a plurality of banks; and a selection circuit for selecting one of the plurality of banks based on the state of the plurality of the fuses and an address signal.

Abstract translation: 半导体存储器件包括多个存储器阵列，其包括多个存储器单元; 多个保险丝，其具有断开状态和连接状态之一，用于将所述多个存储器阵列分类成多个存储体; 以及选择电路，用于基于多个保险丝的状态和地址信号来选择多个存储体中的一个存储体。

公开(公告)号：US06154387A

公开(公告)日：2000-11-28

申请号：US249477

申请日：1999-02-12

Applicant: Hidekazu Takata

Inventor： Hidekazu Takata

IPC: G11C14/00 ,  G11C11/22

CPC classification number: G11C11/22

Abstract: The semiconductor memory device of this invention includes a capacitor, a first transistor, and a second transistor, wherein the capacitor includes a first electrode, a second electrode opposing the first electrode, and a ferroelectric film sandwiched by the first and second electrodes, and stores and holds binary information utilizing a polarizing state of the ferroelectric film, the first transistor includes a first electrode, a second electrode, and a gate electrode, the second electrode being connected to the first electrode of the capacitor, and the second transistor includes a first electrode, a second electrode, and a gate electrode, the first electrode being connected to the second electrode of the capacitor.

Abstract translation: 本发明的半导体存储器件包括电容器，第一晶体管和第二晶体管，其中电容器包括第一电极，与第一电极相对的第二电极和由第一和第二电极夹持的铁电体膜，并且存储 并且利用铁电体膜的极化状态保持二进制信息，第一晶体管包括第一电极，第二电极和栅电极，第二电极连接到电容器的第一电极，第二晶体管包括第一电极 电极，第二电极和栅电极，第一电极连接到电容器的第二电极。

公开(公告)号：US6041015A

公开(公告)日：2000-03-21

申请号：US73228

申请日：1998-05-05

Applicant: Yasuo Miyamoto ,  Hidekazu Takata

Inventor： Yasuo Miyamoto ,  Hidekazu Takata

IPC: G11C11/41 ,  G11C7/10 ,  G11C8/04 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C8/00

CPC classification number: G11C7/1045 ,  G11C7/1018 ,  G11C8/04

Abstract: A semiconductor type memory device includes: a counting unit for receiving a start address and counting an address taking the start address as a starting point; a setting unit for outputting an ending address; and a stopping unit for receiving the counted address and the ending address and causing the counting unit to stop counting when the counted address reaches the ending address.

Abstract translation: 一种半导体型存储装置，包括：计数单元，用于接收开始地址并对以起始地址为起点的地址进行计数; 设置单元，用于输出结束地址; 以及停止单元，用于接收所计数的地址和结束地址，并且当计数的地址到达结束地址时使计数单元停止计数。

公开(公告)号：US5777921A

公开(公告)日：1998-07-07

申请号：US821024

申请日：1997-03-19

Applicant: Hidekazu Takata ,  Hidehiko Tanaka

Inventor： Hidekazu Takata ,  Hidehiko Tanaka

IPC: G11C14/00 ,  G11C7/00 ,  G11C11/22 ,  G11C11/406

CPC classification number: G11C7/00 ,  G11C11/22 ,  G11C11/223

Abstract: A non-volatile semiconductor memory device includes a plurality of memory cells each including a capacitor as a memory element, the capacitor sandwiching a ferroelectric member. The non-volatile semiconductor memory device further includes: a first counter for counting the number of write accesses and read accesses for writing or reading first logic data to each one of the plurality of memory cells; a second counter for counting the number of write accesses and read accesses for writing or reading second logic data to the memory cell; and a refresh control circuit for performing, when either a first value counted by the first counter or a second value counted by the second counter exceeds a predetermined value, a refresh operation by applying electric fields for causing a polarization state of the ferroelectric member of the capacitor to make a complete round on a hysteresis curve of the ferroelectric member in a corresponding one of the plurality of memory cells for which the first or second value counted by the first counter or the second counter has exceeded the predetermined value.

Abstract translation: 非挥发性半导体存储器件包括多个存储单元，每个存储单元包括作为存储元件的电容器，夹着铁电元件的电容器。 所述非易失性半导体存储器件还包括：第一计数器，用于对所述多个存储单元中的每一个写入或读取第一逻辑数据的写访问次数和读访问数进行计数; 第二计数器，用于计数用于将第二逻辑数据写入或读取到存储器单元的写访问次数和读访问次数; 以及刷新控制电路，用于当通过第一计数器计数的第一值或由第二计数器计数的第二值超过预定值时执行刷新操作，通过施加电场来引起铁电元件的极化状态 电容器，用于在由第一计数器或第二计数器计数的第一或第二值超过预定值的多个存储单元中的对应的一个存储单元中的铁电元件的滞后曲线上完成一整圆。