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1.发明授权Controlling voltage levels applied to access devices when accessing storage cells in a memory 有权控制访问存储器中的存储单元时访问设备的电压电平公开(公告)号：US08355276B2
公开(公告)日：2013-01-15
申请号：US12591511
申请日：2009-11-20
CPC分类号： G11C11/413
摘要： A semiconductor memory storage device is disclosed. This memory device has a plurality of storage cells for storing data; a plurality of access devices for allowing access to the corresponding plurality of storage cells, the plurality of access devices being arranged in at least two groups, each of the at least two groups being controlled by an access control line; access control circuitry for controlling a voltage level supplied to a selected one of at least two of the access control lines during access to the storage cell, the access control circuitry comprising a capacitor and switching circuitry; and control circuitry responsive to a data access request to access a selected storage cell to: connect a selected one of the access control lines to a voltage level to allow access via one of the access devices to the selected storage cell; and to control the switching circuitry of the access control circuitry to connect the capacitor of the access control circuitry to the selected access control line and thereby change the voltage level supplied to the selected access control line.
摘要翻译： 公开了一种半导体存储器存储装置。 该存储装置具有用于存储数据的多个存储单元; 用于允许访问对应的多个存储单元的多个访问设备，所述多个访问设备被布置成至少两组，所述至少两个组中的每一个由访问控制线控制; 访问控制电路，用于在访问存储单元期间控制提供给至少两个访问控制线路中的所选择的一个的电压电平，所述访问控制电路包括电容器和开关电路; 以及响应于数据访问请求以访问所选存储单元的控制电路，以将所述访问控制线中的所选择的一个连接到电压电平，以允许经由所述访问设备之一访问所选择的存储单元; 并且控制访问控制电路的切换电路以将访问控制电路的电容器连接到所选择的访问控制线，从而改变提供给所选择的访问控制线路的电压电平。
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公开(公告)号：US08004913B2
公开(公告)日：2011-08-23
申请号：US12801066
申请日：2010-05-20
IPC分类号： G11C7/00
CPC分类号： G11C29/848 , G11C29/808
摘要： An integrated circuit memory includes multiple memory banks grouped into repair groups Group0, Group1. One memory has redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.
摘要翻译： 集成电路存储器包括分组为修复组Group0，Group1的多个存储体。 一个存储器具有冗余行，其可以用于替代在相关公共修复组内的任何存储体中找到的缺陷行。 存储器单元的冗余列可以通过复用电路代替缺陷列。 该多路复用电路将选择的位线移位以形成位组的一部分，以访问给定数据位的量小于该复用电路所支持的多路复用宽度，从而减少需要提供的冗余列的数量。
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公开(公告)号：US20080259701A1
公开(公告)日：2008-10-23
申请号：US11785583
申请日：2007-04-18
IPC分类号： G11C29/04
CPC分类号： G11C29/848 , G11C29/808
摘要： An integrated circuit memory 2 is described having multiple memory banks 4, 6, 8, 10, 12, 14, 16, 18 which are grouped into repair groups Group0, Group1. One of the memory banks 4, 18 is provided with redundant rows 20, 22 which can be used to substitute for a defective row 30, 32, 34 found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells 60, 62 are also provided and these may be substituted for defective columns 66, 68 by multiplexing circuitry 56, 58. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry 56, 58 thereby reducing the number of redundant columns which need be provided.
摘要翻译： 描述了具有多个存储体组4,6,8,10,12,14,16,18的集成电路存储器2，它们分组成维修组组0，组1。 存储器组4,18中的一个设置有冗余行20,22，其可用于替代在相关公共修复组内的任何存储体中发现的有缺陷的行30,32,34。 还提供了存储单元60,62的冗余列，并且它们可以通过复用电路56,58来代替缺陷列66,68。 该多路复用电路将选择的位线移位以形成位组的一部分，以访问给定数据位小于多路复用电路56,58支持的多路复用宽度的量，从而减少需要的冗余列数 提供。
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公开(公告)号：US08830783B2
公开(公告)日：2014-09-09
申请号：US12929138
申请日：2011-01-03
申请人： Sachin Satish Idgunji , Hemangi Umakant Gajjewar , Vincent Phillipe Schuppe , Yew Keong Chong , Hsin-Yu Chen
发明人： Sachin Satish Idgunji , Hemangi Umakant Gajjewar , Vincent Phillipe Schuppe , Yew Keong Chong , Hsin-Yu Chen
IPC分类号： G11C8/00 , G11C11/419 , G11C11/418 , G11C11/41 , G11C11/413 , G11C8/08 , G11C7/22 , G11C8/10 , G11C8/16 , G11C11/412
CPC分类号： G11C7/222 , G11C8/08 , G11C8/10 , G11C8/16 , G11C11/41 , G11C11/412 , G11C11/413 , G11C11/418 , G11C11/419
摘要： A semiconductor memory storage device is disclosed. The memory comprises a plurality of storage cells for storing data each storage cell comprising an access control device for providing the storage cell with access to or isolation from a data access port in response to an access control signal, access control circuitry for transmitting the access control signal along an access control line to control a plurality of the access control devices connected to the access control line. The access control circuitry responds to a data access request signal by increasing a voltage level supplied to the access control line to a first voltage level at a first average rate and then in response to receipt of a further signal increasing the voltage level supplied to the access control line to the predetermined higher voltage level, in such a way that a further average rate of increase of the voltage level from the first to the predetermined higher voltage level is lower than the first average rate of increase to the first level.
摘要翻译： 公开了一种半导体存储器存储装置。 存储器包括用于存储数据的多个存储单元，每个存储单元包括访问控制设备，用于响应于访问控制信号向存储单元提供对数据访问端口的访问或与数据访问端口的隔离，存取控制电路用于发送访问控制 信号沿着访问控制线路控制连接到访问控制线路的多个访问控制设备。 访问控制电路通过将提供给访问控制线的电压电平以第一平均速率增加到第一电压电平来响应于数据访问请求信号，然后响应于接收到增加提供给访问的电压电平的另外的信号 控制线到预定的较高电压电平，使得从第一电压到预定的较高电压电平的电压电平的进一步的平均增加率低于第一平均增长率至第一电平。
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公开(公告)号：US20110187438A1
公开(公告)日：2011-08-04
申请号：US12926966
申请日：2010-12-20
摘要： An integrated circuit, method of controlling power supplied to semiconductor devices, a method of designing an integrated circuit and a computer program product are disclosed. The integrated circuit comprises: a semiconductor device for handling data; a power source for powering said semiconductor device, said power source comprising a high voltage source for supplying a high voltage level and a low voltage source for supplying a low voltage level; a plurality of switching devices arranged between at least one of the high or low voltage sources and the semiconductor device. There is also a control device for controlling a first set of the plurality of switching devices to connect one of the high or low voltage sources to the semiconductor device and for controlling a second set of the plurality of switching devices to connect the one of the high or low voltage sources to the semiconductor device. At least some of the first set of the plurality of switching devices have a higher resistance when closed and providing a connection than at least some of the second set of the plurality of switching devices such that when the first set of the plurality of switching devices connect the semiconductor device to the one of the voltage sources the semiconductor device operates with a lower performance than when the second set of the plurality of switching devices connect the semiconductor device to the one of said voltage sources.
摘要翻译： 公开了集成电路，控制提供给半导体器件的功率的方法，集成电路的设计方法和计算机程序产品。 集成电路包括：用于处理数据的半导体器件; 用于为所述半导体器件供电的电源，所述电源包括用于提供高电压电平的高电压源和用于提供低电压电平的低电压源; 布置在所述高压或低电压源中的至少一个与所述半导体器件之间的多个开关器件。 还有一个控制装置，用于控制多个开关装置的第一组，以将高压或低压源中的一个连接到半导体装置，并且用于控制多个开关装置的第二组，以连接高压 或低电压源。 多个开关装置的第一组中的至少一些在闭合时具有较高的电阻，并且提供与多个开关装置的第二组中的至少一些的连接，使得当多个开关装置中的第一组连接时 所述半导体器件至所述电压源中的一个电压源，所述半导体器件以比所述多个开关器件的所述第二组将所述半导体器件连接到所述电压源中的一个的性能更低的性能来操作。
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公开(公告)号：US07924638B2
公开(公告)日：2011-04-12
申请号：US11785583
申请日：2007-04-18
IPC分类号： G11C7/00
CPC分类号： G11C29/848 , G11C29/808
摘要： An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group0, Group1. One of the memory banks is provided with redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells are also provided and these may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.
摘要翻译： 描述了具有多个存储体的集成电路存储器，其被分组为维修组Group0，Group1。 其中一个存储器组被提供有冗余的行，其可用于替代在相关公共修复组内的任何存储体中找到的有缺陷的行。 还提供了存储器单元的冗余列，并且这些列可以通过复用电路代替缺陷列。 该多路复用电路移位被选择以形成位组的一部分的位线，以访问给定数据位小于该多路复用电路支持的多路复用宽度的量，从而减少需要提供的冗余列的数量。
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7.发明申请Controlling voltage levels applied to access devices when accessing storage cells in a memory 有权控制访问存储器中的存储单元时访问设备的电压电平公开(公告)号：US20110122712A1
公开(公告)日：2011-05-26
申请号：US12591511
申请日：2009-11-20
CPC分类号： G11C11/413
摘要： A semiconductor memory storage device is disclosed. This memory device has a plurality of storage cells for storing data; a plurality of access devices for allowing access to the corresponding plurality of storage cells, the plurality of access devices being arranged in at least two groups, each of the at least two groups being controlled by an access control line; access control circuitry for controlling a voltage level supplied to a selected one of at least two of the access control lines during access to the storage cell, the access control circuitry comprising a capacitor and switching circuitry; and control circuitry responsive to a data access request to access a selected storage cell to: connect a selected one of the access control lines to a voltage level to allow access via one of the access devices to the selected storage cell; and to control the switching circuitry of the access control circuitry to connect the capacitor of the access control circuitry to the selected access control line and thereby change the voltage level supplied to the selected access control line.
摘要翻译： 公开了一种半导体存储器存储装置。 该存储装置具有用于存储数据的多个存储单元; 用于允许访问对应的多个存储单元的多个访问设备，所述多个访问设备被布置成至少两组，所述至少两个组中的每一个由访问控制线控制; 访问控制电路，用于在访问存储单元期间控制提供给至少两个访问控制线路中的所选择的一个的电压电平，所述访问控制电路包括电容器和开关电路; 以及响应于数据访问请求以访问所选存储单元的控制电路，以将所述访问控制线中的所选择的一个连接到电压电平，以允许经由所述访问设备之一访问所选择的存储单元; 并且控制访问控制电路的切换电路以将访问控制电路的电容器连接到所选择的访问控制线，从而改变提供给所选择的访问控制线路的电压电平。
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公开(公告)号：US07606057B2
公开(公告)日：2009-10-20
申请号：US11443443
申请日：2006-05-31
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C7/1048 , G11C7/18 , H01L27/1104
摘要： A memory cell includes polysilicon gates 2 running in a first direction. A sequence of layers metal lines includes a layer of bit lines 4 running in a second direction substantially orthogonal to the first direction followed by data lines 6 running in that second direction and then word lines 8 running in the first direction. The data lines 6 are precharged to a value which is held whilst the bit lines 4 are being used to sense data values stored within a memory cell.
摘要翻译： 存储单元包括在第一方向上运行的多晶硅栅极2。 一层层金属线包括沿与第一方向大致正交的第二方向运行的位线4，随后是在该第二方向上运行的数据线6，然后在第一方向上运行的字线8。 数据线6被预充电到在位线4被用于感测存储在存储器单元中的数据值时被保持的值。
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公开(公告)号：US08582389B2
公开(公告)日：2013-11-12
申请号：US13067629
申请日：2011-06-15
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C8/16 , G11C11/419
摘要： A semiconductor memory storage device with a plurality of storage cells, each cell includes two access control devices, each providing the cell with access to or isolation from a respective one of two data lines in response to an access control signal provided by access control circuitry. The control devices are controlled to provide the storage cell with access to or isolation from either of the first and second of the two data lines. The access control circuitry is responsive to a data access request, the data access request being a write request, to apply a data value to be written to both of the first and second data lines and to apply the access control signal to both of the first and second access control lines.
摘要翻译： 一种具有多个存储单元的半导体存储器存储设备，每个单元包括两个访问控制设备，每个存储控制设备响应于由访问控制电路提供的访问控制信号，为每个单元提供对两个数据线中的相应一个的访问或隔离的单元。 控制设备被控制以向存储单元提供对两条数据线中的第一和第二数据线中的任一条的访问或隔离。 访问控制电路响应于数据访问请求，数据访问请求是写请求，以将要写入的数据值应用于第一和第二数据线，并将访问控制信号应用于第一 和第二存取控制线。
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公开(公告)号：US20120170390A1
公开(公告)日：2012-07-05
申请号：US12929138
申请日：2011-01-03
申请人： Sachin Satish Idgunji , Hemangi Umakant Gajjewar , Vincent Phillipe Schuppe , Yew Keong Chong , Hsin-Yu Chen
发明人： Sachin Satish Idgunji , Hemangi Umakant Gajjewar , Vincent Phillipe Schuppe , Yew Keong Chong , Hsin-Yu Chen
CPC分类号： G11C7/222 , G11C8/08 , G11C8/10 , G11C8/16 , G11C11/41 , G11C11/412 , G11C11/413 , G11C11/418 , G11C11/419
摘要： A semiconductor memory storage device is disclosed. The memory comprises a plurality of storage cells for storing data each storage cell comprising an access control device for providing the storage cell with access to or isolation from a data access port in response to an access control signal, access control circuitry for transmitting the access control signal along an access control line to control a plurality of the access control devices connected to the access control line. The access control circuitry responds to a data access request signal by increasing a voltage level supplied to the access control line to a first voltage level at a first average rate and then in response to receipt of a further signal increasing the voltage level supplied to the access control line to the predetermined higher voltage level, in such a way that a further average rate of increase of the voltage level from the first to the predetermined higher voltage level is lower than the first average rate of increase to the first level.
摘要翻译： 公开了一种半导体存储器存储装置。 存储器包括用于存储数据的多个存储单元，每个存储单元包括访问控制设备，用于响应于访问控制信号向存储单元提供对数据访问端口的访问或与数据访问端口的隔离，存取控制电路用于发送访问控制 信号沿着访问控制线路控制连接到访问控制线路的多个访问控制设备。 访问控制电路通过将提供给访问控制线的电压电平以第一平均速率增加到第一电压电平来响应于数据访问请求信号，然后响应于接收到增加提供给访问的电压电平的另外的信号 控制线到预定的较高电压电平，使得从第一电压到预定的较高电压电平的电压电平的进一步的平均增加率低于第一平均增长率至第一电平。
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