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    Polarized stereoscopic display device and method
    2.
    发明授权
    Polarized stereoscopic display device and method 有权
    极化立体显示装置及方法

    公开(公告)号：US08289380B2

    公开(公告)日：2012-10-16

    申请号：US11514617

    申请日：2006-08-31

    Applicant: Eun-Soo Kim ,  Seung-Cheol Kim

    Inventor： Eun-Soo Kim ,  Seung-Cheol Kim

    IPC: H04N13/00 ,  H04N13/04

    CPC classification number: G02B27/26 ,  H04N13/139 ,  H04N13/324 ,  H04N13/337 ,  H04N13/363

    Abstract: The present invention relates to a polarized stereoscopic display method and a device thereof. In one embodiment, the device comprises a first signal processing part for signal processing the first image and producing a first input image that is input to a first projector so that a first output beam output from the first projector corresponding to the first image is output from the first projector with a 90 degree phase difference with respect to a second output beam outputted from the second projector corresponding to the second image. The first signal processing part may comprise an image rotating part for rotating an inputted image by 90 degree, a resizing part combined with an output terminal of the image rotating part for resizing the image rotated by 90 degree corresponding to a screen and output it to the first projector.

    Abstract translation: 本发明涉及一种偏振立体显示方法及其装置。 在一个实施例中，设备包括第一信号处理部分，用于对第一图像进行信号处理并产生输入到第一投影仪的第一输入图像，使得从第一投影仪输出的与第一图像对应的第一输出光束从 相对于从第二投影仪输出的对应于第二图像的第二输出光束具有90度相位差的第一投影仪。 第一信号处理部分可以包括用于将输入图像旋转90度的图像旋转部分，与图像旋转部分的输出端相结合的调整大小部分，用于调整对应于屏幕旋转90度的图像的大小，并将其输出到 第一台投影机

    Method of manufacturing semiconductor devices having metal lines
    3.
    发明授权
    Method of manufacturing semiconductor devices having metal lines 有权
    制造具有金属线的半导体器件的方法

    公开(公告)号：US08216932B2

    公开(公告)日：2012-07-10

    申请号：US12345611

    申请日：2008-12-29

    Applicant: Cheol Mo Jeong ,  Eun Soo Kim ,  Seung Hee Hong

    Inventor： Cheol Mo Jeong ,  Eun Soo Kim ,  Seung Hee Hong

    IPC: H01L21/4763

    CPC classification number: H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention relates to semiconductor devices and a method of fabricating the same. According to a method of manufacturing semiconductor devices, there is first provided a semiconductor substrate in which a first pre-metal dielectric layer including trenches is formed. A diffusion barrier layer is formed on the entire surface including the trenches. A metal layer is formed on the diffusion barrier layer including the trenches, thereby gap-filling the trenches. A polish etching process is performed on the metal layer and the diffusion barrier layer so that the diffusion barrier layer and the metal layer remain within the trenches. An etching process of lowering a height of the metal layer is performed in order to increase a distance between metal lines. A capping layer is formed on the entire surface including exposed sidewalls of the first pre-metal dielectric layer. A second pre-metal dielectric layer is formed over the capping layer.

    Abstract translation: 本发明涉及半导体器件及其制造方法。 根据制造半导体器件的方法，首先提供其中形成包括沟槽的第一预金属电介质层的半导体衬底。 在包括沟槽的整个表面上形成扩散阻挡层。 在包括沟槽的扩散阻挡层上形成金属层，从而间隙填充沟槽。 在金属层和扩散阻挡层上进行抛光蚀刻工艺，使得扩散阻挡层和金属层保留在沟槽内。 执行降低金属层的高度的蚀刻工艺，以增加金属线之间的距离。 在包括第一预金属介电层的暴露的侧壁的整个表面上形成覆盖层。 在覆盖层上方形成第二预金属介电层。

    AUTOMATIC MOVING APPARATUS FOR PRE-CRASH HEADREST
    4.
    发明申请
    AUTOMATIC MOVING APPARATUS FOR PRE-CRASH HEADREST 有权
    自动移动装置用于预先冲洗头

    公开(公告)号：US20120013155A1

    公开(公告)日：2012-01-19

    申请号：US12956747

    申请日：2010-11-30

    Applicant: Su Hwan HWANG ,  Bong Joon Lee ,  Eun Soo Kim ,  Gil Ju Kim ,  Jun Yeol Heo ,  Jong Kweon Pyun ,  In Ho Lee ,  Seung Jai Kim ,  Do Hyoung Kim ,  Sang Nam Park ,  Dong Gi Kim ,  Jin Young Nam

    Inventor： Su Hwan HWANG ,  Bong Joon Lee ,  Eun Soo Kim ,  Gil Ju Kim ,  Jun Yeol Heo ,  Jong Kweon Pyun ,  In Ho Lee ,  Seung Jai Kim ,  Do Hyoung Kim ,  Sang Nam Park ,  Dong Gi Kim ,  Jin Young Nam

    IPC: B60N2/427

    CPC classification number: B60N2/002 ,  B60N2/829 ,  B60N2/888

    Abstract: An automatic moving apparatus may include a collision prediction sensor, a control unit comparing a value measured by the collision prediction sensor, with a reference value stored in the control unit, and outputting a control signal when it may be determined that the value measured by the collision prediction sensor is higher than the reference value, and a headrest moving unit moving a headrest unit toward a passenger's head before the headrest unit comes into contact with the passenger's head, and including a stay rod connected to the headrest unit, both sides of the stay rod being placed in a vertical direction, tilting device tilting the stay rod forwards or backwards relative to a seatback in response to the control signal of the control unit, and vertical moving device moving the stay rod in a vertical direction in response to the control signal of the control unit.

    Abstract translation: 自动移动装置可以包括碰撞预测传感器，控制单元，将由碰撞预测传感器测量的值与存储在控制单元中的参考值进行比较，并且当可以确定由 碰撞预测传感器高于参考值，头枕移动单元在头枕单元与乘客头部接触之前将头枕单元移动到乘客头部，并且包括连接到头枕单元的撑杆， 延伸杆被放置在垂直方向上，倾斜装置响应于控制单元的控制信号相对于座椅靠背向前或向后倾斜拉杆，并且垂直移动装置响应于控制而沿垂直方向移动拉杆 控制单元的信号。

    Semiconductor device and method of forming contact plug of semiconductor device
    5.
    发明授权
    Semiconductor device and method of forming contact plug of semiconductor device 有权
    形成半导体器件接触插塞的半导体器件及方法

    公开(公告)号：US07851350B2

    公开(公告)日：2010-12-14

    申请号：US11965368

    申请日：2007-12-27

    Applicant: Whee Won Cho ,  Jung Geun Kim ,  Eun Soo Kim

    Inventor： Whee Won Cho ,  Jung Geun Kim ,  Eun Soo Kim

    IPC: H01L21/4763

    CPC classification number: H01L21/76804 ,  H01L21/76831

    Abstract: The present invention relates to a semiconductor device and a method of forming a contact plug of a semiconductor device. According to the method, a first dielectric layer is formed on a semiconductor substrate in which junction regions are formed. A hard mask is formed on the first dielectric layer. The hard mask and the first dielectric layer corresponding to the junction regions are etched to form trenches. Spacers are formed on sidewalls of the trenches. Contact holes are formed in the first dielectric layer using an etch process employing the spacers and the hard mask so that the junction regions are exposed. The contact holes are gap filled with a conductive material, thus forming contact plugs. Accordingly, bit lines can be easily formed on the contact plugs formed at narrow spaces with a high density.

    Abstract translation: 本发明涉及半导体器件和形成半导体器件的接触插塞的方法。 根据该方法，在形成有接合区域的半导体基板上形成第一电介质层。 在第一电介质层上形成硬掩模。 对应于接合区域的硬掩模和第一介电层被蚀刻以形成沟槽。 间隙形成在沟槽的侧壁上。 使用使用间隔物和硬掩模的蚀刻工艺在第一介电层中形成接触孔，使得接合区域露出。 接触孔用导电材料间隙填充，从而形成接触塞。 因此，可以容易地在高密度的狭窄空间形成的接触塞上形成位线。

    Method of forming bit line of flash memory device
    6.
    发明授权
    Method of forming bit line of flash memory device 有权
    形成闪存器件位线的方法

    公开(公告)号：US07807565B2

    公开(公告)日：2010-10-05

    申请号：US11439527

    申请日：2006-05-22

    Applicant: Woo Yung Jung ,  Tae Kyung Kim ,  Eun Soo Kim

    Inventor： Woo Yung Jung ,  Tae Kyung Kim ,  Eun Soo Kim

    IPC: H01L21/4763 ,  H01L23/12

    CPC classification number: H01L21/76816 ,  H01L21/76804 ,  H01L21/76838 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11521

    Abstract: A method for forming a semiconductor device includes forming drain contact holes in a first interlayer insulating layer provided over a semiconductor substrate. First metal material is formed over the first interlayer insulating layer and fills the drain contact holes. A first metal layer formed by patterning the first metal material includes first lines and landing pads. Trenches formed in a second interlayer insulating layer formed over the patterned first metal material expose the landing pads. A second metal layer is formed by providing second metal material over the second interlayer insulating layer and filling the trenches. The second metal layer includes second lines within the trenches that contact the landing pads. The first and second metal layers define a first metal level of the semiconductor device. The first lines define odd-number lines of the first metal level, and the second lines define even-number lines of the first metal level.

    Abstract translation: 一种形成半导体器件的方法包括在设置在半导体衬底上的第一层间绝缘层中形成漏极接触孔。 第一金属材料形成在第一层间绝缘层上并填充漏极接触孔。 通过图案化第一金属材料形成的第一金属层包括第一线和着陆焊盘。 形成在图案化的第一金属材料上的第二层间绝缘层中形成的沟槽露出着陆焊盘。 通过在第二层间绝缘层上提供第二金属材料并填充沟槽来形成第二金属层。 第二金属层包括沟槽内的接触着陆焊盘的第二线。 第一和第二金属层限定半导体器件的第一金属层。 第一行定义第一金属级的奇数行，第二行定义第一金属级的偶数行。

    Method of forming a metal line of a semiconductor device
    7.
    发明授权
    Method of forming a metal line of a semiconductor device 失效
    形成半导体器件的金属线的方法

    公开(公告)号：US07601632B2

    公开(公告)日：2009-10-13

    申请号：US11646925

    申请日：2006-12-27

    Applicant: Eun Soo Kim ,  Cheol Mo Jeong ,  Seung Hee Hong

    Inventor： Eun Soo Kim ,  Cheol Mo Jeong ,  Seung Hee Hong

    IPC: H01L21/00

    CPC classification number: H01L21/76882 ,  H01L21/76838 ,  H01L21/76865 ,  H01L21/76879

    Abstract: A first conductive layer is formed over a substrate in which contact holes are formed in an interlayer insulating layer. The first conductive layer is melted by an annealing process, thus coating the lower sidewalls of the contact holes and partially filling the contact holes. A second conductive layer is deposited with a method having selectivity with respect to the same material as the first conductive layer, thus fully filling the contact holes. A metal line is formed on the second conductive layer. The contact holes are completely filled with a conductive material and the load of a CMP process can be alleviated. Accordingly, the electrical characteristics of a device can be improved, process reliability can be improved, and process repeatablity can be improved.

    Abstract translation: 在层间绝缘层中形成有接触孔的基板上形成第一导电层。 第一导电层通过退火工艺熔化，从而涂覆接触孔的下侧壁并部分填充接触孔。 以与第一导电层相同的材料具有选择性的方法沉积第二导电层，从而完全填充接触孔。 金属线形成在第二导电层上。 接触孔完全充满导电材料，可以减轻CMP工艺的负荷。 因此，可以提高器件的电气特性，提高工艺可靠性，提高加工的可重复性。

    Method of forming metal line of semiconductor memory device
    8.
    发明授权
    Method of forming metal line of semiconductor memory device 失效
    形成半导体存储器件金属线的方法

    公开(公告)号：US07557033B2

    公开(公告)日：2009-07-07

    申请号：US11647087

    申请日：2006-12-27

    Applicant: Eun Soo Kim ,  Seung Hee Hong ,  Cheol Mo Jeong ,  Jung Geun Kim

    Inventor： Eun Soo Kim ,  Seung Hee Hong ,  Cheol Mo Jeong ,  Jung Geun Kim

    IPC: H01L21/4763

    CPC classification number: H01L21/76834 ,  H01L21/32139 ,  H01L21/76837

    Abstract: A method of forming a metal line of a semiconductor memory device includes the steps of forming plugs of a damascene structure in a first interlayer insulating layer over a semiconductor substrate, forming a barrier metal layer, a metal layer and an anti-reflection layer on the resulting surface, etching the anti-reflection layer, the metal layer, and the barrier metal layer according a specific pattern, and forming an insulating layer on sidewalls of the metal layer.

    Abstract translation: 形成半导体存储器件的金属线的方法包括以下步骤：在半导体衬底上的第一层间绝缘层中形成镶嵌结构的插塞，在其上形成阻挡金属层，金属层和抗反射层 根据特定图案蚀刻抗反射层，金属层和阻挡金属层，并在金属层的侧壁上形成绝缘层。

    METHOD FOR FORMING A METAL LINE IN A SEMICONDUCTOR DEVICE
    9.
    发明申请
    METHOD FOR FORMING A METAL LINE IN A SEMICONDUCTOR DEVICE 失效
    在半导体器件中形成金属线的方法

    公开(公告)号：US20090053889A1

    公开(公告)日：2009-02-26

    申请号：US12053488

    申请日：2008-03-21

    Applicant: Seung Hee Hong ,  Jung Geun Kim ,  Eun Soo Kim

    Inventor： Seung Hee Hong ,  Jung Geun Kim ,  Eun Soo Kim

    IPC: H01L21/4763

    CPC classification number: H01L21/76877 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76847 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes contact plugs formed in contact holes defined in an interlayer dielectric. Upper portions of the contact plugs are etched. A first barrier layer is formed on a surface of the interlayer dielectric including the contact plugs. A second barrier layer is formed on the first barrier layer over the interlayer dielectric. The second barrier layer has lower compatibility with a metallic material than the first barrier layer. A first metal layer is formed over the first and second barrier layers. The first metal layer, the first barrier layer and the second barrier layer are then patterned.

    Abstract translation: 半导体器件包括形成在层间电介质中限定的接触孔中的接触塞。 接触塞的上部被蚀刻。 在包括接触塞的层间电介质的表面上形成第一阻挡层。 在层间电介质上的第一阻挡层上形成第二阻挡层。 与第一阻挡层相比，第二阻挡层与金属材料的相容性较低。 在第一和第二阻挡层上形成第一金属层。 然后对第一金属层，第一阻挡层和第二阻挡层进行图案化。

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