公开(公告)号：US20090140385A1

公开(公告)日：2009-06-04

申请号：US12288880

申请日：2008-10-24

Applicant: Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

Inventor： Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

IPC: H01L29/00

CPC classification number: B82Y10/00 ,  H01G4/005 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

Abstract translation: 提供了一种具有纳米管的电容器及其制造方法。 所述电容器包括：下电极，其包括图案化导电层和形成在所述图案化导电层上的多个纳米管，所述多个纳米管不需要使用催化剂层; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。 该方法包括以下步骤：形成用于形成下电极的导电层; 在不使用催化剂层的情况下形成包括形成在所述导电层上的多个纳米管的纳米管阵列; 在纳米管阵列上形成介电层; 以及在所述电介质层上形成上电极。

公开(公告)号：US07387929B2

公开(公告)日：2008-06-17

申请号：US11271601

申请日：2005-11-10

Applicant: Eun A. Lee ,  Hai Won Kim

Inventor： Eun A. Lee ,  Hai Won Kim

IPC: H01L21/8242

CPC classification number: H01L28/40

Abstract: The present invention relates to a capacitor in semiconductor device and a method of manufacturing the same, wherein, owing to formation of a lower electrode and an upper electrode into a stack structure of a poly-silicon layer and an aluminum (Al) layer and formation of an alumina (Al2O3) film as a dielectric film, the lower electrode is formed into a stack structure of the poly-silicon layer-aluminum (Al) layer, thus increasing a surface area of electrodes due to the absence of oxidation during annealing, and preventing degeneration of the device, and use of the dielectric film including a high-dielectric constant material layer enables reduction of the dielectric film's thickness. Accordingly, the present invention is capable of increasing capacitance, is capable of reducing leakage current and improving dielectric breakdown characteristics via internal formation of an MIM capacitor, and is capable of reducing production costs by performing a continuous process via use of a single piece of equipment.

公开(公告)号：US20080081430A1

公开(公告)日：2008-04-03

申请号：US11758507

申请日：2007-06-05

Applicant: Cheol Hwan Park ,  Dong-Su Park ,  Eun A. Lee ,  Hye Jin Seo

Inventor： Cheol Hwan Park ,  Dong-Su Park ,  Eun A. Lee ,  Hye Jin Seo

IPC: H01L21/24

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: A method for forming a capacitor in a semiconductor device is disclosed. The method includes forming a storage node electrode on a semiconductor substrate, forming a dielectric layer having a high dielectric constant on the storage node electrode, depositing a plate electrode on the dielectric layer, thereby forming by-product impurities, and removing by-product impurities remaining on the plate electrode by introducing a hydrogen (H) atom-containing gas onto the semiconductor substrate while depositing a capping layer on the plate electrode.

Abstract translation: 公开了一种在半导体器件中形成电容器的方法。 该方法包括在半导体衬底上形成存储节点电极，在存储节点电极上形成具有高介电常数的电介质层，在电介质层上沉积平板电极，从而形成副产物杂质，除去副产物杂质 通过在半导体衬底上引入含氢（H）原子的气体，同时在平板电极上沉积覆盖层而残留在平板电极上。

公开(公告)号：US20080003751A1

公开(公告)日：2008-01-03

申请号：US11646730

申请日：2006-12-28

Applicant: Cheol Hwan Park ,  Dong Su Park ,  Eun A. Lee ,  Hye Jin Seo

Inventor： Cheol Hwan Park ,  Dong Su Park ,  Eun A. Lee ,  Hye Jin Seo

IPC: H01L21/336

CPC classification number: H01L21/82345 ,  H01L21/28044 ,  H01L21/324 ,  H01L21/823842

Abstract: A method for forming a dual poly gate of a semiconductor device includes forming a gate insulating layer on a semiconductor substrate having a first region and a second region; forming an amorphous silicon layer, in which a portion defined by the first region is implanted with impurity ions of a first conductivity type and a portion defined by the second region is implanted with impurity ions of a second conductivity type, on the gate insulating layer; forming silicon seeds on the amorphous silicon layer; forming hemispherical grains on the surface of the amorphous silicon layer using the silicon seeds; and activating the implanted impurity ions and crystallizing the amorphous silicon layer having the hemispherical grains formed thereon by annealing to form a polysilicon layer of a first conductivity type and a polysilicon layer of a second conductivity type in the portions of the amorphous silicon layer defined by the first and second regions, respectively.

Abstract translation: 一种用于形成半导体器件的双多晶硅栅极的方法包括在具有第一区域和第二区域的半导体衬底上形成栅极绝缘层; 形成非晶硅层，其中由栅极绝缘层注入由第一导电类型的杂质离子和由第二区限定的部分，由第一区限定的部分注入第二导电类型的杂质离子; 在所述非晶硅层上形成硅晶种; 使用硅晶粒在非晶硅层的表面上形成半球状晶粒; 并激活注入的杂质离子并使其上形成有半球形晶粒的非晶硅层通过退火结晶，以在由非晶硅层限定的部分中形成第一导电类型的多晶硅层和第二导电类型的多晶硅层 第一和第二区域。

公开(公告)号：US07300852B2

公开(公告)日：2007-11-27

申请号：US11089122

申请日：2005-03-24

Applicant: Ho Jin Cho ,  Jun Soo Chang ,  Eun A. Lee ,  Su Jin Chae ,  Young Dae Kim

Inventor： Ho Jin Cho ,  Jun Soo Chang ,  Eun A. Lee ,  Su Jin Chae ,  Young Dae Kim

IPC: H01L21/20

CPC classification number: H01L21/02312 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/3144 ,  H01L28/60

Abstract: A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace under a nitride atmosphere to eliminate stress generated by the RTN; forming Al2O3 and HfO2 dielectric films on the nitrified bottom electrode; and forming a plate electrode of the capacitor on the Al2O3 and HfO2 dielectric films. The thermal process is performed after the RTN performed on the surface of the bottom electrode, so that stress, generated from the RTN, is alleviated, thereby allowing the capacitor to obtain a high capacitance and lowering leakage current.

Abstract translation: 一种制造半导体元件的电容器的方法，包括：在半导体衬底上形成电容器的底部电极; 在底电极的上表面进行快速热硝化（RTN）; 对所获得的在氮化物气氛下的炉中具有底部电极的结构进行热处理以消除由RTN产生的应力; 在硝化的底部电极上形成Al 2 O 3 N 3和HfO 2 N 2电介质膜; 以及在Al 2 O 3和HfO 2 N 2电介质膜上形成电容器的平板电极。 在底电极表面进行RTN之后进行热处理，从而可以减轻由RTN产生的应力，从而使电容器获得高电容，降低漏电流。

公开(公告)号：US06955974B2

公开(公告)日：2005-10-18

申请号：US10877714

申请日：2004-06-25

Applicant: Tae Hyeok Lee ,  Cheol Hwan Park ,  Dong Su Park ,  Ho Jin Cho ,  Eun A Lee

Inventor： Tae Hyeok Lee ,  Cheol Hwan Park ,  Dong Su Park ,  Ho Jin Cho ,  Eun A Lee

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8242

CPC classification number: H01L21/76224 ,  H01L27/10894

Abstract: A method for forming an isolation layer of a semiconductor device, which comprises the steps of: a) sequentially forming a pad oxide layer and a pad nitride layer on a silicon substrate; b) etching the pad nitride layer, the pad oxide layer, and the silicon substrate, thereby forming a trench; c) thermal-oxidizing the resultant substrate to form a sidewall oxide layer on a surface of the trench; d) nitrifying the sidewall oxide layer through the use of NH3 annealing; e) depositing a liner aluminum nitride layer on an entire surface of the silicon substrate inclusive of the nitrated sidewall oxide layer; f) depositing a buried oxide layer on the liner aluminum nitride layer to fill the trench; g) performing a chemical mechanical polishing process with respect to the buried oxide layer; and h) eliminating the pad nitride layer.

Abstract translation: 一种用于形成半导体器件的隔离层的方法，包括以下步骤：a）在硅衬底上依次形成焊盘氧化物层和衬垫氮化物层; b）蚀刻衬垫氮化物层，衬垫氧化物层和硅衬底，从而形成沟槽; c）热氧化所得衬底以在沟槽的表面上形成侧壁氧化物层; d）通过使用NH 3退火对侧壁氧化物层进行硝化; e）在包括所述硝化侧壁氧化物层的所述硅衬底的整个表面上沉积衬里氮化铝层; f）在衬里氮化铝层上沉积掩埋氧化物层以填充沟槽; g）对所述掩埋氧化物层进行化学机械抛光工艺; 以及h）消除所述衬垫氮化物层。

公开(公告)号：US07463476B2

公开(公告)日：2008-12-09

申请号：US11148057

申请日：2005-06-07

Applicant: Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

Inventor： Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

IPC: H01G4/06

CPC classification number: B82Y10/00 ,  H01G4/005 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

Abstract translation: 提供了一种具有纳米管的电容器及其制造方法。 所述电容器包括：下电极，其包括图案化导电层和形成在所述图案化导电层上的多个纳米管，所述多个纳米管不需要使用催化剂层; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。 该方法包括以下步骤：形成用于形成下电极的导电层; 在不使用催化剂层的情况下形成包括形成在所述导电层上的多个纳米管的纳米管阵列; 在纳米管阵列上形成介电层; 以及在所述电介质层上形成上电极。

公开(公告)号：US20080242045A1

公开(公告)日：2008-10-02

申请号：US11951965

申请日：2007-12-06

Applicant: Keum Bum LEE ,  Dong Su Park ,  Jun Soo Chang ,  Eun A Lee

Inventor： Keum Bum LEE ,  Dong Su Park ,  Jun Soo Chang ,  Eun A Lee

IPC: H01L21/62

CPC classification number: H01L21/76232

Abstract: A method for fabricating a trench dielectric layer in a semiconductor device is provided. A trench is formed in a semiconductor substrate and a liner nitride layer is then formed on an inner wall of the trench. A liner oxide layer formed on the liner nitride layer is nitrified in order to protect the liner nitride layer from being exposed. Subsequently, the trench is filled with one or more dielectric layers.

Abstract translation: 提供一种在半导体器件中制造沟槽电介质层的方法。 在半导体衬底中形成沟槽，然后在沟槽的内壁上形成衬里氮化物层。 形成在衬里氮化物层上的衬里氧化物层被硝化以保护衬里氮化物层免受暴露。 随后，沟槽被一个或多个电介质层填充。

公开(公告)号：US20060221548A1

公开(公告)日：2006-10-05

申请号：US11148057

申请日：2005-06-07

Applicant: Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

Inventor： Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

IPC: H01G4/228

CPC classification number: B82Y10/00 ,  H01G4/005 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

公开(公告)号：US07688570B2

公开(公告)日：2010-03-30

申请号：US12288880

申请日：2008-10-24

Applicant: Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

Inventor： Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

IPC: H01G4/06

CPC classification number: B82Y10/00 ,  H01G4/005 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

Abstract translation: 提供了一种具有纳米管的电容器及其制造方法。 所述电容器包括：下电极，其包括图案化导电层和形成在所述图案化导电层上的多个纳米管，所述多个纳米管不需要使用催化剂层; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。 该方法包括以下步骤：形成用于形成下电极的导电层; 在不使用催化剂层的情况下形成包括形成在所述导电层上的多个纳米管的纳米管阵列; 在纳米管阵列上形成介电层; 以及在所述电介质层上形成上电极。