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    Data security for dynamic random access memory using body bias to clear data at power-up
    1.
    发明授权
    Data security for dynamic random access memory using body bias to clear data at power-up 有权
    使用身体偏倚的动态随机存取存储器的数据安全性，以在上电时清除数据

    公开(公告)号：US08467230B2

    公开(公告)日：2013-06-18

    申请号：US12898924

    申请日：2010-10-06

    申请人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Michael Launsbach ,  Daniel Mark Nelson

    发明人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Michael Launsbach ,  Daniel Mark Nelson

    IPC分类号： G11C11/24

    CPC分类号： G11C7/24 ,  G11C5/145 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4078

    摘要： A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.

    摘要翻译： 电路和方法在上电时擦除存储在DRAM芯片中的所有数据，以提高数据安全性。 通过增加单元的体电压同时接通DRAM存储单元的晶体管，可以擦除所有的DRAM存储单元。 在示例电路中，通过由对存储器单元的p阱施加电压的上电复位（POR）信号控制的电荷泵增加体电压。 向p阱施加的电压降低了电池的阈值电压，使得存储器单元的NFET晶体管将导通。 当所有设备都打开时，存储在存储单元中的数据将被擦除，因为连接到通用位线的所有单元的电压合并为单个值。

    Delay chain burn-in for increased repeatability of physically unclonable functions
    2.
    发明授权
    Delay chain burn-in for increased repeatability of physically unclonable functions 失效
    延迟链老化可增加物理不可克隆功能的重复性

    公开(公告)号：US08159260B1

    公开(公告)日：2012-04-17

    申请号：US12898044

    申请日：2010-10-05

    申请人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Daniel Mark Nelson

    发明人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Daniel Mark Nelson

    IPC分类号： H03K19/00 ,  G06F11/30 ,  G06F13/00

    CPC分类号： G06F7/588 ,  H04L9/0866

    摘要： A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.

    摘要翻译： 电路和方法通过在芯片烧录期间通过两个延迟链增强信号延迟的变化来增加物理上不可检测的功能（PUF）的重复性。 老化电路在老化过程中将两个延迟链的输入保持相反的随机值。 延迟链中所有在输入端具有低电平值的PFET将以更高的导通电压进行烧录。 由于在两个延迟链中受影响的PFET在老化期间被相反的转变驱动，所以两个延迟链中的延迟组件的交替组合受老化周期的影响。 在正常操作下，两个延迟链看到相同的输入，所以只有一个链延迟增加，以实现两个延迟路径的统计上可靠的差异，从而增加了PUF电路的整体重复性。

    DELAY CHAIN BURN-IN FOR INCREASED REPEATABILITY OF PHYSICALLY UNCLONABLE FUNCTIONS
    3.
    发明申请
    DELAY CHAIN BURN-IN FOR INCREASED REPEATABILITY OF PHYSICALLY UNCLONABLE FUNCTIONS 失效
    延迟链燃烧以增加物理不可靠功能的重复性

    公开(公告)号：US20120081143A1

    公开(公告)日：2012-04-05

    申请号：US12898044

    申请日：2010-10-05

    申请人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Daniel Mark Nelson

    发明人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Daniel Mark Nelson

    IPC分类号： H03K19/00

    CPC分类号： G06F7/588 ,  H04L9/0866

    摘要： A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.

    摘要翻译： 电路和方法通过在芯片烧录期间通过两个延迟链增强信号延迟的变化来增加物理上不可检测的功能（PUF）的重复性。 老化电路在老化过程中将两个延迟链的输入保持相反的随机值。 延迟链中所有在输入端具有低电平值的PFET将以更高的导通电压进行烧录。 由于在两个延迟链中受影响的PFET在老化期间被相反的转变驱动，所以两个延迟链中的延迟组件的交替组合受老化周期的影响。 在正常操作下，两个延迟链看到相同的输入，所以只有一个链延迟增加，以实现两个延迟路径的统计上可靠的差异，从而增加了PUF电路的整体重复性。

    APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION
    5.
    发明申请
    APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION 失效
    用于实现SRAM单元写入性能评估的设备

    公开(公告)号：US20090116298A1

    公开(公告)日：2009-05-07

    申请号：US12351920

    申请日：2009-01-12

    申请人： Chad Allen Adams ,  Derick Gardner Behrends ,  Travis Reynold Hebig ,  Daniel Mark Nelson

    发明人： Chad Allen Adams ,  Derick Gardner Behrends ,  Travis Reynold Hebig ,  Daniel Mark Nelson

    IPC分类号： G11C7/00

    CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C2029/1202

    摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.

    摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。 环形振荡器电路用于产生字线脉冲。 状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。 将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。 然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。 从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

    Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and Required Number of Redundant Elements
    6.
    发明申请
    Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and Required Number of Redundant Elements 审中-公开
    方法和增强型SRAM冗余电路，用于减少接线和所需的冗余元件数量

    公开(公告)号：US20080112219A1

    公开(公告)日：2008-05-15

    申请号：US11868575

    申请日：2007-10-08

    申请人： Derick Gardner Behrends ,  Peter Thomas Freiburger ,  Ryan Charles Kivimagi ,  Daniel Mark Nelson

    发明人： Derick Gardner Behrends ,  Peter Thomas Freiburger ,  Ryan Charles Kivimagi ,  Daniel Mark Nelson

    IPC分类号： G11C11/34

    CPC分类号： G11C29/846

    摘要： A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements, and a design structure on which the subject SRAM redundancy circuit resides is provided. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.

    摘要翻译： 一种方法和增强的静态随机存取存储器（SRAM）冗余电路减少了布线和所需数量的冗余元件，并且提供了存在被摄体SRAM冗余电路的设计结构。 位线冗余机制允许对一对位列进行交换。 两个相邻的位线一次被换出，一个偶数和一个奇数。 交换是通过围绕不良列操作数据进行转换，并在需要时引导的末尾添加冗余列。

    High performance read bypass test for SRAM circuits
    9.
    发明授权
    High performance read bypass test for SRAM circuits 失效
    SRAM电路的高性能读取旁路测试

    公开(公告)号：US07751266B2

    公开(公告)日：2010-07-06

    申请号：US12146777

    申请日：2008-06-26

    申请人： Chad Allen Adams ,  Derick Gardner Behrends ,  Daniel Mark Nelson ,  Jeffrey Milton Scherer

    发明人： Chad Allen Adams ,  Derick Gardner Behrends ,  Daniel Mark Nelson ,  Jeffrey Milton Scherer

    IPC分类号： G11C29/00

    CPC分类号： G11C29/12 ,  G11C11/41 ,  G11C29/1201

    摘要： A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode.

    摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构和用于BIST（内置自检）的高性能SRAM（静态随机存取存储器）读取旁路的集成电路。 该设计结构和集成结构包括用于SRAM阵列的读取输出的动态到静态转换单元和集成到动态到静态转换单元中的测试旁路单元，以便允许SRAM阵列的读取输出通过 在不影响性能的非测试模式下，并绕过SRAM阵列的读取输出，并允许测试信号在测试模式下通过。

    DELAY MECHANISM FOR UNBALANCED READ/WRITE PATHS IN DOMINO SRAM ARRAYS
    10.
    发明申请
    DELAY MECHANISM FOR UNBALANCED READ/WRITE PATHS IN DOMINO SRAM ARRAYS 有权
    多米诺SRAM阵列中不平衡读/写缓存的延迟机制

    公开(公告)号：US20080117695A1

    公开(公告)日：2008-05-22

    申请号：US11560428

    申请日：2006-11-16

    申请人： Chad Allen Adams ,  Anthony Gus Aipperspach ,  Derick Gardner Behrends ,  George Francis Paulik

    发明人： Chad Allen Adams ,  Anthony Gus Aipperspach ,  Derick Gardner Behrends ,  George Francis Paulik

    IPC分类号： G11C7/00 ,  G11C8/10

    CPC分类号： G11C8/10

    摘要： A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_wl and write_wl signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_wl signal and an output for outputting a delayed version of the write_wl signal. The wordline signal is activated by the wordline decoder based on the read_wl signal and the delayed write_wl signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.

    摘要翻译： 存储器系统，例如多米诺骨牌静态随机存取存储器（SRAM），包括多个存储器单元和通过字线耦合到存储器单元的字线解码器。 字线解码器通过字线向一个或多个存储器单元提供字线信号，以允许访问存储器单元用于读取操作或写入操作。 Read_wl和write_wl信号由字线解码器基于在下一周期中是执行读操作还是写操作生成。 字线解码器包括具有用于接收write_wl信号的输入的缓冲器和用于输出write_wl信号的延迟版本的输出。 基于read_wl信号和延迟的write_wl信号，字线信号由字线解码器激活。 这克服了由于快速读取路径而导致写入性能下降的“早期读取”问题。