公开(公告)号：US20100022208A1

公开(公告)日：2010-01-28

申请号：US12575455

申请日：2009-10-07

Applicant: Jean-Pierre Joseph Cole ,  David A. Rowe ,  Craig A. Hornbuckle

Inventor： Jean-Pierre Joseph Cole ,  David A. Rowe ,  Craig A. Hornbuckle

IPC: H04B1/04

CPC classification number: H04B17/14 ,  H04B7/08 ,  H04B17/101 ,  H04B17/104

Abstract: An example of a radio frequency (RF) transmitter system for communication may include a transmit pre-distortion module configured to provide a second transmit calibration signal during a transmit calibration mode based on a first transmit calibration signal and one or more transmit calibration adjustment signals. The one or more transmit calibration adjustment signals may include an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances. The system may include a transmit channel frequency converter coupled to the transmit pre-distortion module. The transmit channel frequency converter may be configured to provide a fourth transmit calibration signal during the transmit calibration mode based on a third transmit calibration signal and a transmit reference signal.

Abstract translation: 用于通信的射频（RF）发射机系统的示例可以包括被配置为在发射校准模式期间基于第一发射校准信号和一个或多个发射校准调整信号来提供第二发射校准信号的发射预失真模块。 一个或多个发射校准调整信号可以包括与DC偏移相关联的偏移参数和与增益和相位不平衡中的至少一个相关联的不平衡参数。 该系统可以包括耦合到发射预失真模块的发射信道频率转换器。 发射信道频率转换器可以被配置为基于第三发射校准信号和发射参考信号在发射校准模式期间提供第四发射校准信号。

公开(公告)号：US07286572B2

公开(公告)日：2007-10-23

申请号：US10338972

申请日：2003-01-10

Applicant: Craig A. Hornbuckle ,  David A. Rowe ,  Thomas W. Krawczyk, Jr. ,  Samuel A. Steidl ,  Inho Kim

Inventor： Craig A. Hornbuckle ,  David A. Rowe ,  Thomas W. Krawczyk, Jr. ,  Samuel A. Steidl ,  Inho Kim

IPC: H04J3/02

CPC classification number: H04J3/0685 ,  H04J3/047 ,  Y10S370/907

Abstract: An integrated circuit includes a serdes framer interface (SFI) circuit for receiving a first set of data channels and a reference channel, generating first logic levels for the first set of data channels, and realigning the first set of data channels relative to a reference channel. The integrated circuit further includes a multiplexing circuit for receiving a second set of data channels and for merging the second set of data channels into one or more data channels. The second set of data channels is generated based on the first set of data channels. A data rate of the one or more data channels is higher than a data rate of the second set of data channels.

Abstract translation: 集成电路包括用于接收第一组数据信道和参考信道的serdes成帧器接口（SFI）电路，为第一组数据信道生成第一逻辑电平，并相对于参考信道重新对准第一组数据信道 。 集成电路还包括多路复用电路，用于接收第二组数据信道并将第二组数据信道合并成一个或多个数据信道。 基于第一组数据信道生成第二组数据信道。 一个或多个数据信道的数据速率高于第二组数据信道的数据速率。

公开(公告)号：US06950485B2

公开(公告)日：2005-09-27

申请号：US10329739

申请日：2002-12-26

Applicant: James L. Richards ,  Preston L. Jett ,  Larry W. Fullerton ,  Lawrence E. Larson ,  David A. Rowe

Inventor： James L. Richards ,  Preston L. Jett ,  Larry W. Fullerton ,  Lawrence E. Larson ,  David A. Rowe

IPC: H03L7/00 ,  G01S7/282 ,  G01S13/02 ,  G01S13/10 ,  H03D3/24 ,  H03K5/135 ,  H03L7/18 ,  H04B20060101 ,  H04B1/69 ,  H04B14/02 ,  H04J3/06 ,  H04L1/08 ,  H04L7/00 ,  H04L7/08 ,  H04L25/40

CPC classification number: H04B1/7183 ,  G01S7/282 ,  G01S13/0209 ,  G01S13/106 ,  H03L7/18 ,  H04B1/71635 ,  H04L1/08

Abstract: A precision timing generator includes a combiner that provides a timing signal by combining a coarse timing signal and a fine timing signal derived from a phase-shifted sinusoidal signal that has a desired phase shift. The coarse timing generator generates the coarse timing signal from a clock signal and a timing command input. The fine timing generator includes a sinusoidal-signal generator that receives the clock signal and generates a sinusoidal signal. The fine timing generator also includes a phase shifter that receives the sinusoidal signal and the timing command input and shifts the phase of the sinusoidal signal based on the timing input to generate the phase shifted sinusoidal signal.

Abstract translation: 精确定时发生器包括组合器，其通过组合粗定时信号和从具有期望相移的相移正弦信号导出的精细定时信号来提供定时信号。 粗定时发生器从时钟信号和定时命令输入产生粗定时信号。 精确定时发生器包括正弦信号发生器，其接收时钟信号并产生正弦信号。 精确定时发生器还包括接收正弦信号和定时指令输入的移相器，并且基于定时输入偏移正弦信号的相位，以产生相移的正弦信号。

公开(公告)号：US06803252B2

公开(公告)日：2004-10-12

申请号：US09990247

申请日：2001-11-21

Applicant: Binneg Y. Lao ,  William W. Chen ,  David A. Rowe ,  Inho Kim

Inventor： Binneg Y. Lao ,  William W. Chen ,  David A. Rowe ,  Inho Kim

IPC: H01L2144

CPC classification number: H01L23/66 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2223/6638 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1903 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Methods and apparatus for providing connection packages for high-speed integrated circuits (“ICs”) in optical, electronic, wired or wireless communications are disclosed. The connection package achieves dimensional transformation of signal routes from high-speed, high-density IC's input/output pads to the external terminals such as coaxial terminals and BGA balls, while maintaining constant characteristic impedance throughout the transmission lines. A package may include a substrate having microstrips for communicating signals between the IC pads and external terminals. A pair of differential microstrips can be positioned closer to each other near the IC pads and create capacitive coupling. Such coupled capacitance allows the width of the microstrips to be reduced. A portion of the coupled microstrips near the IC pads can be widened to increase the capacitance so that the overall transmission path can become an all-pass network—from the IC pads, through the bonding wires, to the microstrips. The rest of the portions of the microstrips can be tapered out to their respective external connectors. In addition, a multi-layer package may include a substrate, at least one coaxial external terminal formed at the side of the package for conducting a high-speed signal, BGA connectors formed at the bottom of the package for conducting low-speed signals, a microstrip for connecting the high-speed signal to the coaxial terminal, and microstrips and internal coaxial connectors for connecting the low-speed signals to the BGA connectors. Substantially constant characteristic impedance is achieved throughout the signal transmission paths in the package.

Abstract translation: 公开了用于为光学，电子，有线或无线通信中的高速集成电路（“IC”）提供连接封装的方法和装置。 连接封装实现了从高速，高密度IC输入/输出焊盘到诸如同轴端子和BGA球的外部端子的信号路线的尺寸变换，同时在整个传输线路上保持恒定的特性阻抗。 封装可以包括具有用于在IC焊盘和外部端子之间传递信号的微带的衬底。 一对差分微带可以靠近IC焊盘更靠近，并产生电容耦合。 这种耦合电容允许微带的宽度减小。 IC焊盘附近的耦合微带的一部分可以加宽以增加电容，使得整个传输路径可以成为从IC焊盘，通过接合线到微带的全通网络。 微带的其余部分可以锥形到它们各自的外部连接器。 此外，多层封装可以包括衬底，形成在封装侧的用于传导高速信号的至少一个同轴外部端子，形成在封装底部的用于传导低速信号的BGA连接器， 用于将高速信号连接到同轴端子的微带，以及用于将低速信号连接到BGA连接器的微带和内部同轴连接器。 在封装中的整个信号传输路径中实现了基本恒定的特性阻抗。

公开(公告)号：US06636573B2

公开(公告)日：2003-10-21

申请号：US09954201

申请日：2001-09-18

Applicant: James L Richards ,  Preston Jett ,  Larry W Fullerton ,  Lawrence E Larson ,  David A Rowe

Inventor： James L Richards ,  Preston Jett ,  Larry W Fullerton ,  Lawrence E Larson ,  David A Rowe

IPC: H04L700

CPC classification number: H03L7/18 ,  H04B1/7163 ,  H04B1/71635 ,  H04B1/7183

Abstract: A frame reference signal is produced as a function of a clock signal. A first timing generator generates a coarse timing signal having a nominal period and a transition occurring at a precise temporal position with respect to the nominal period. The nominal period is a function of the frame reference signal. The temporal position is a function of a first input timing command and the clock signal. A second timing generator generates at least one fine timing transition as a function of a second input timing command and the clock signal. A combiner circuit uses the coarse timing signal to select one of the at least one fine timing transitions to output a precise timing signal, wherein the precise timing signal has a high temporal precision with respect to the frame reference signal.

公开(公告)号：US06509801B1

公开(公告)日：2003-01-21

申请号：US09895955

申请日：2001-06-29

Applicant: Binneg Y. Lao ,  David A. Rowe ,  James R. Pulver

Inventor： Binneg Y. Lao ,  David A. Rowe ,  James R. Pulver

IPC: H03L700

CPC classification number: H04L7/033 ,  H03L7/0896 ,  H03L7/14

Abstract: Methods and apparatus for generating clock signals accurately locked to multi-gigabits-per-second data signals received over fiber optic channels are disclosed. The invention includes a phase detector for comparing a data signal and a clock signal, a one shot unit for detecting a data transition, an XOR, a filter, a main charge pump, a compensating charge pump for producing additive or compensating current, and a VCO for generating the clock signal. The phase detector includes multiple D-flip flops. The one shot unit includes a delay unit and an AND gate. The filter includes a resistor, a capacitor and a negative resistance amplifier. The main charge pump includes differential inputs, double outputs, cross-quading resistors, differential NPN input transistors, and a current source. The compensating charge pump includes differential NPN input transistors and a current source. In operation, when there is a data transition and if the clock signal and data signal are out of phase synchronization, then the compensating charge pump will enhance the operation of the main charge pump, and the VCO will speed up or slow down the clock signal depending on whether the clock signal is advanced or retarded in phase compared to the data signal. When there is no data transition, the compensating charge pump will in effect counterbalance the operation of the main charge pump, and the frequency of the clock signal will be maintained at the same level it was at the onset of the no data transition period.

Abstract translation: 公开了用于产生准确地锁定在通过光纤通道接收的每千兆比特数据信号的时钟信号的方法和装置。 本发明包括用于比较数据信号和时钟信号的相位检测器，用于检测数据转换的单触发单元，XOR，滤波​​器，主电荷泵，用于产生添加剂或补偿电流的补偿电荷泵，以及 VCO用于产生时钟信号。 相位检测器包括多个D触发器。 一次性单元包括延迟单元和与门。 滤波器包括电阻器，电容器和负电阻放大器。 主电荷泵包括差分输入，双输出，交叉电阻，差分NPN输入晶体管和电流源。 补偿电荷泵包括差分NPN输入晶体管和电流源。 在运行中，当存在数据转换，如果时钟信号和数据信号异相同步，则补偿电荷泵将增强主电荷泵的运行，并且VCO将加速或减慢时钟信号 取决于时钟信号与数据信号相比是高速还是延迟。 当没有数据转换时，补偿电荷泵实际上将平衡主电荷泵的运行，并且时钟信号的频率将保持在无数据转换周期开始的同一电平。

公开(公告)号：US06421389B1

公开(公告)日：2002-07-16

申请号：US09356384

申请日：1999-07-16

Applicant: Preston Jett ,  Lawrence E. Larson ,  Bret A. Pollack ,  David A. Rowe

Inventor： Preston Jett ,  Lawrence E. Larson ,  Bret A. Pollack ,  David A. Rowe

IPC: H04L2700

CPC classification number: H04L25/4902 ,  H04B1/71637 ,  H04B1/7183 ,  H04B1/719

Abstract: A baseband signal converter device for an impulse radio receiver combines multiple converter circuits and an RF amplifier in a single integrated circuit package. Each converter circuit includes an integrator circuit that integrates a portion of each RF pulse during a sampling period triggered by a timing pulse generator. The integrator capacitor is isolated by a pair of Schottky diodes connected to a pair of load resistors. A current equalizer circuit equalizes the current flowing through the load resistors when the integrator is not sampling. Current steering logic transfers load current between the diodes and a constant bias circuit depending on whether a sampling pulse is present.

Abstract translation: 用于脉冲无线电接收机的基带信号转换器装置将多个转换器电路和RF放大器组合在单个集成电路封装中。 每个转换器电路包括积分器电路，其在由定时脉冲发生器触发的采样周期期间对每个RF脉冲的一部分进行积分。 积分器电容由一对连接到一对负载电阻的肖特基二极管隔离。 当积分器不采样时，电流均衡器电路均衡流过负载电阻器的电流。 电流转向逻辑根据是否存在采样脉冲，传输二极管之间的负载电流和恒定偏置电路。

公开(公告)号：US3956140A

公开(公告)日：1976-05-11

申请号：US355153

申请日：1973-04-27

Applicant: James Jang Woo Nahm ,  David A. Rowe

Inventor： James Jang Woo Nahm ,  David A. Rowe

IPC: C09K8/24 ,  C09K7/02

CPC classification number: C09K8/24 ,  Y10S507/925 ,  Y10S516/03

Abstract: Well drilling, workover and completion fluids containing various water soluble condensation products of phenolic materials, formaldehyde and sulfite salts. Such condensation products may be further modified by including during the condensation reaction one or more of urea, melamine, salicylic acid, benzoic acid, phthalic acid, adipic acid, succinic acid, glutaric acid, maleic acid or the anhydrides of said acids. The drilling, workover or completion fluids may also contain clay-dispersants.

Abstract translation: 钻井，修井和完井液含有酚类物质，甲醛和亚硫酸盐的各种水溶性缩合产物。 可以通过在缩合反应中包含尿素，三聚氰胺，水杨酸，苯甲酸，邻苯二甲酸，己二酸，琥珀酸，戊二酸，马来酸或所述酸的酸酐中的一种或多种来包含这样的缩合产物。 钻井，修井或完井液也可能含有粘土分散剂。

公开(公告)号：US08593221B1

公开(公告)日：2013-11-26

申请号：US13300500

申请日：2011-11-18

Applicant: Liping Zhang ,  Thomas W. Krawczyk ,  Andrew J. Bonthron ,  David A. Rowe

Inventor： Liping Zhang ,  Thomas W. Krawczyk ,  Andrew J. Bonthron ,  David A. Rowe

IPC: H03F3/45

CPC classification number: H03F3/45085 ,  H03F3/45484 ,  H03F2203/45244

Abstract: Examples of circuits and methods are provided for common mode stability and bandwidth broadening. A current generator circuit may include a first and a second transistor. Each of the first and second transistors includes a first, second, and third terminal. The first and second transistors provide a first and a second output current at their corresponding third terminals. A first branch including a first resistor and a first capacitor coupled in series is coupled between the third terminal of the first transistor and the first terminal of the second transistor. A second branch including a second resistor and a second capacitor coupled in series is coupled between the third terminal of the second transistor and the first terminal of the first transistor. The first and the second branches are configured to enable the current generator circuit to provide the first and second currents with improved common mode stability.

Abstract translation: 提供了电路和方法的示例，用于共模稳定性和带宽拓宽。 电流发生器电路可以包括第一和第二晶体管。 第一和第二晶体管中的每一个包括第一，第二和第三端子。 第一和第二晶体管在其相应的第三端提供第一和第二输出电流。 包括第一电阻器和串联耦合的第一电容器的第一支路耦合在第一晶体管的第三端子和第二晶体管的第一端子之间。 包括串联耦合的第二电阻器和第二电容器的第二支路耦合在第二晶体管的第三端子和第一晶体管的第一端子之间。 第一和第二分支被配置为使得电流发生器电路能够提供改善的共模稳定性的第一和第二电流。

公开(公告)号：US07974593B2

公开(公告)日：2011-07-05

申请号：US12575455

申请日：2009-10-07

Applicant: Jean-Pierre Joseph Cole ,  David A. Rowe ,  Craig A. Hornbuckle

Inventor： Jean-Pierre Joseph Cole ,  David A. Rowe ,  Craig A. Hornbuckle

IPC: H04B1/06 ,  H04K3/00

CPC classification number: H04B17/14 ,  H04B7/08 ,  H04B17/101 ,  H04B17/104

Abstract: An example of a radio frequency (RF) transmitter system for communication may include a transmit pre-distortion module configured to provide a second transmit calibration signal during a transmit calibration mode based on a first transmit calibration signal and one or more transmit calibration adjustment signals. The one or more transmit calibration adjustment signals may include an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances. The system may include a transmit channel frequency converter coupled to the transmit pre-distortion module. The transmit channel frequency converter may be configured to provide a fourth transmit calibration signal during the transmit calibration mode based on a third transmit calibration signal and a transmit reference signal.

Abstract translation: 用于通信的射频（RF）发射机系统的示例可以包括被配置为在发射校准模式期间基于第一发射校准信号和一个或多个发射校准调整信号来提供第二发射校准信号的发射预失真模块。 一个或多个发射校准调整信号可以包括与DC偏移相关联的偏移参数和与增益和相位不平衡中的至少一个相关联的不平衡参数。 该系统可以包括耦合到发射预失真模块的发射信道频率转换器。 发射信道频率转换器可以被配置为基于第三发射校准信号和发射参考信号在发射校准模式期间提供第四发射校准信号。