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    Optical high speed communications for a computed tomography x-ray machine
    2.
    发明授权
    Optical high speed communications for a computed tomography x-ray machine 失效
    计算机断层扫描X光机的光学高速通信

    公开(公告)号：US06396613B1

    公开(公告)日：2002-05-28

    申请号：US09218638

    申请日：1998-12-22

    申请人： Daniel David Harrison ,  Deva Narayan Pattanayak

    发明人： Daniel David Harrison ,  Deva Narayan Pattanayak

    IPC分类号： H04B1012

    CPC分类号： A61B6/56 ,  H04B10/801

    摘要： A computed tomography system employs an optical communications link to reliably transmit high data rate data. The communications link comprises an optical emitter, an optical transmission line, a plurality of optical deflectors disposed randomly within the transmission line, and an optical receiver. The optical emitter is attached to the gantry of the computed tomography system and extends along the length of the gantry. The optical emitter generates a high data rate optical data signal, which travels along the optical transmission line in correspondence with data generated by detector array on the gantry. The plurality of optical deflectors causes portions the high data rate optical data signal to be internally reflected and subsequently refracted from the transmission line. The optical receiver disposed near the transmission line detects the portion of high data rate data refracted from the transmission line.

    摘要翻译： 计算机断层摄影系统采用光通信链路可靠地传输高数据速率数据。 通信链路包括光发射器，光传输线，随机地布置在传输线内的多个光偏转器和光接收器。 光发射器连接到计算机断层摄影系统的台架，并沿着台架的长度延伸。 光发射器产生高数据速率光学数据信号，其沿着光传输线行进，与机架上的检测器阵列产生的数据相对应。 多个光学偏转器使得高数据速率光学数据信号的内部部分被内部反射并随后从传输线折射。 设置在传输线附近的光接收器检测从传输线折射的高数据速率数据的部分。

    Integrate and fold analog-to-digital converter with saturation prevention
    3.
    发明授权
    Integrate and fold analog-to-digital converter with saturation prevention 失效
    集成和折叠具有饱和度预防的模数转换器

    公开(公告)号：US06366231B1

    公开(公告)日：2002-04-02

    申请号：US09546623

    申请日：2000-04-10

    申请人： Naresh Kesavan Rao ,  Daniel David Harrison ,  Donald Thomas McGrath ,  Jerome Johnson Tiemann

    发明人： Naresh Kesavan Rao ,  Daniel David Harrison ,  Donald Thomas McGrath ,  Jerome Johnson Tiemann

    IPC分类号： H03M150

    CPC分类号： H03M1/141 ,  H03M1/1215 ,  H03M1/60

    摘要： An analog to digital conversion circuit for converting an analog input signal into a plurality of binary output bits includes an operational amplifier and an integrating capacitor for storing a charge proportional to the integral of the input signal. A charge subtracting circuit removes a first predetermined charge from the integrating capacitor when an output charge of the operational amplifier is substantially equal to a second predetermined charge. The first predetermined charge level is removed from the integrating capacitor a number of times. The removal of the first predetermined charge from the integrating capacitor allows the integral of the analog input signal to be larger than a maximum charge capable of being stored by the integrating capacitor. A digital logic circuit tracks the number of times that the first predetermined charge is removed from the integrating capacitor by the charge subtracting circuit, and the digital logic circuit provides at least one bit of the plurality of binary output bits. A residue quantizing circuit determines a residual charge in the integrating capacitor and provides at least one additional bit of the plurality of binary output bits corresponding to the residual charge. The residual charge is substantially equal to a stored charge in the integrating capacitor after the first predetermined charge has been removed the number of times.

    摘要翻译： 用于将模拟输入信号转换成多个二进制输出位的模数转换电路包括运算放大器和用于存储与输入信号的积分成比例的电荷的积分电容器。 当运算放大器的输出电荷基本上等于第二预定电荷时，电荷减去电路从积分电容器去除第一预定电荷。 第一预定电荷电平从积分电容器中多次去除。 从积分电容器去除第一预定电荷允许模拟输入信号的积分大于能够由积分电容器存储的最大电荷。 数字逻辑电路跟踪由电荷减法电路从积分电容器去除第一预定电荷的次数，数字逻辑电路提供多个二进制输出位的至少一位。 残余量化电路确定积分电容器中的残余电荷，并提供与剩余电荷相对应的多个二进制输出位中的至少一个附加位。 残余电荷基本上等于在第一预定电荷已被去除次数之后积分电容器中的存储电荷。

    GPS receiver for emergency location reporting during intermittent shadowing
    7.
    发明授权
    GPS receiver for emergency location reporting during intermittent shadowing 有权
    GPS接收器用于间歇性遮蔽期间的紧急位置报告

    公开(公告)号：US06298229B1

    公开(公告)日：2001-10-02

    申请号：US09206722

    申请日：1998-12-04

    申请人： Harold Woodruff Tomlinson, Jr. ,  Daniel David Harrison

    发明人： Harold Woodruff Tomlinson, Jr. ,  Daniel David Harrison

    IPC分类号： H04M1100

    CPC分类号： G01S19/17 ,  G01S5/0036 ,  G01S19/34 ,  H04B1/3805

    摘要： A controller in a mobile telephone periodically commands GPS circuitry in the mobile telephone to power-on, capture and process GPS satellite signals. The signals are processed to obtain pseudo-range or time-difference data for at least one GPS satellite. After the signals are processed, the pseudo-range or time-difference data, GPS time, and satellite numbers are stored in non-volatile random access memory (RAM) and the GPS circuitry is powered off. When an emergency signal is present, the controller first commands the GPS circuitry to power-on, capture and process signals from four GPS satellites. If signals from at least four satellites are not present, the information stored in non-volatile RAM is read out. The processed data (if available), or else the data read out of the non-volatile RAM, are reported to a central location through the mobile telephone transmitter. The central location can then use the data to compute the present or last valid GPS location of the GPS receiver. The periodic sampling of the GPS signal minimizes power consumption and obtains a valid GPS location before shadowing occurs.

    摘要翻译： 移动电话中的控制器周期性地命令移动电话中的GPS电路进行上电，捕获和处理GPS卫星信号。 处理信号以获得用于至少一个GPS卫星的伪距或时差数据。 在处理信号之后，伪距或时差数据，GPS时间和卫星号被存储在非易失性随机存取存储器（RAM）中，并且GPS电路断电。 当存在紧急信号时，控制器首先命令GPS电路从四个GPS卫星上电，捕获和处理信号。 如果不存在来自至少四颗卫星的信号，则读出存储在非易失性RAM中的信息。 经处理的数据（如果可用），或者从非易失性RAM读出的数据，通过移动电话发送器报告给中央位置。 然后，中央位置可以使用该数据来计算GPS接收机的当前或最后有效的GPS位置。 GPS信号的周期性采样可以最大限度地降低功耗，并在发生遮蔽之前获得有效的GPS位置。

    Multi-phase programmable clock generator
    8.
    发明授权
    Multi-phase programmable clock generator 失效
    多相可编程时钟发生器

    公开(公告)号：US06246275B1

    公开(公告)日：2001-06-12

    申请号：US09441323

    申请日：1999-11-16

    申请人： Robert Gideon Wodnicki ,  Paul Andrew Frank ,  Donald Thomas McGrath ,  Daniel David Harrison

    发明人： Robert Gideon Wodnicki ,  Paul Andrew Frank ,  Donald Thomas McGrath ,  Daniel David Harrison

    IPC分类号： H03K300

    CPC分类号： H03K5/135 ,  H03K5/24

    摘要： The present invention provides a clocked comparator which extends the time period before an input signal is measured to include most of the clock cycle, thereby increasing the amount of time available for the input signal to achieve a “steady-state” condition. After the input signal achieves a “steady-state” condition the comparator compares the input signal against a reference voltage and a decision register latches the comparator output. The decision signal may then be further latched to be made available for external circuitry in the subsequent clock cycle. A multi-phase programmable signal generator is connected to the clocked generator for generating a plurality of timing signals. The multi-phase programmable signal generator employs a plurality of single bit registers interconnected in series to form a shift register. Output signals generated by the programmable signal generator are used to drive the switches and register clocks of the clocked comparator.

    摘要翻译： 本发明提供了一种时钟比较器，其延长了在测量输入信号之前的时间段以包括大部分时钟周期，从而增加了可用于输入信号以实现“稳态”状态的时间量。 在输入信号达到“稳态”状态之后，比较器将输入信号与参考电压进行比较，并且决定寄存器锁存比较器输出。 然后可以进一步锁定该决定信号以在随后的时钟周期内使外部电路可用。 多相可编程信号发生器连接到时钟发生器，用于产生多个定时信号。 多相可编程信号发生器采用串联互连的多个单位寄存器来形成移位寄存器。 由可编程信号发生器产生的输出信号用于驱动定时比较器的开关和寄存器时钟。

    Apparatus and method for a high frequency clocked comparator and apparatus for multi-phase programmable clock generator
    10.
    发明授权
    Apparatus and method for a high frequency clocked comparator and apparatus for multi-phase programmable clock generator 失效
    一种用于多相可编程时钟发生器的高频时钟比较器和装置的装置和方法

    公开(公告)号：US6037809A

    公开(公告)日：2000-03-14

    申请号：US89604

    申请日：1998-06-02

    申请人： Robert Gideon Wodnicki ,  Paul Andrew Frank ,  Donald Thomas McGrath ,  Daniel David Harrison

    发明人： Robert Gideon Wodnicki ,  Paul Andrew Frank ,  Donald Thomas McGrath ,  Daniel David Harrison

    IPC分类号： H03K5/08 ,  H03K5/135 ,  H03K5/24 ,  H03K5/153

    CPC分类号： H03K5/135 ,  H03K5/24

    摘要： The present invention provides a clocked comparator which extends the time period before an input signal is measured to include most of the clock cycle, thereby increasing the amount of time available for the input signal to achieve a "steady-state" condition. After the input signal achieves a "steady-state" condition the comparator compares the input signal against a reference voltage and a decision register latches the comparator output. The decision signal may then be further latched to be made available for external circuitry in the subsequent clock cycle. A multi-phase programmable signal generator is connected to the clocked generator for generating a plurality of timing signals. The multi-phase programmable signal generator employs a plurality of single bit registers interconnected in series to form a shift register. Output signals generated by the programmable signal generator are used to drive the switches and register clocks of the clocked comparator.

    摘要翻译： 本发明提供了一种时钟比较器，其延长了在测量输入信号之前的时间段以包括大部分时钟周期，从而增加了可用于输入信号以实现“稳态”状态的时间量。 在输入信号达到“稳态”状态之后，比较器将输入信号与参考电压进行比较，并且决定寄存器锁存比较器输出。 然后可以进一步锁定该决定信号以在随后的时钟周期内使外部电路可用。 多相可编程信号发生器连接到时钟发生器，用于产生多个定时信号。 多相可编程信号发生器采用串联互连的多个单位寄存器来形成移位寄存器。 由可编程信号发生器产生的输出信号用于驱动时钟控制比较器的开关和寄存器时钟。