公开(公告)号：US20070076873A1

公开(公告)日：2007-04-05

申请号：US10579136

申请日：2004-11-10

申请人： Nobuyuki Yamamoto ,  Daigo Senoo

发明人： Nobuyuki Yamamoto ,  Daigo Senoo

IPC分类号： H04N7/167

CPC分类号： G11B20/00086 ,  G11B20/0021 ,  G11B20/00333 ,  G11B20/00347 ,  G11B20/00507

摘要： A data processing device of the invention has an ID creator unit (300) which adds ID information which is set by a CPU and the number of sectors, and outputs a result of the addition as ID information; a scramble SEED value table (103) which produces an initial scramble SEED value, by using the ID information which is outputted from the ID creator unit (300); a normal scramble filter (104) which produces a scramble SEED value (402) for data to be transferred; a frame jumping scramble filter (301) which holds a scramble SEED value of a jumping destination (401) in preparation for jumping; and a selector (105) which selects one of the scramble SEED value (401) and the scramble SEED value (402) and outputs the selected value to the normal scramble filter (104). Accordingly, the data processing device can perform a scrambling process and a de-scrambling process, without depending on the reliability of the data being transferred.

摘要翻译： 本发明的数据处理装置具有ID生成单元（300），其添加由CPU设定的ID信息和扇区数，并输出添加结果作为ID信息; 通过使用从ID创建单元（300）输出的ID信息产生初始加扰SEED值的加扰SEED值表（103）; 正常扰频滤波器（104），其产生用于要传送的数据的加扰SEED值（402）; 保持跳跃目的地（401）的加扰SEED值准备跳跃的帧跳跃加扰滤波器（301）; 以及选择器（105），其选择加密SEED值（401）和加密SEED值（402）中的一个，并将所选择的值输出到正常加扰滤波器（104）。 因此，数据处理装置可以执行加扰处理和去加扰处理，而不依赖于正在传送的数据的可靠性。

公开(公告)号：US08196023B2

公开(公告)日：2012-06-05

申请号：US12718490

申请日：2010-03-05

申请人： Daigo Senoo

发明人： Daigo Senoo

IPC分类号： H03M13/00

CPC分类号： H03M13/2954 ,  G11B20/1217 ,  G11B20/1833 ,  G11B20/1866 ,  G11B2020/1267 ,  G11B2020/1836 ,  G11B2020/1846 ,  G11B2220/2541 ,  H03M13/15 ,  H03M13/1515

摘要： An encoder includes an information holding section which stores flag bytes and an initial address, a data generation section which generates sets of first parity symbols from the initial address and the flag bytes, a parity generation section which generates and outputs sets of second parity symbols, for each column of data units included in the block, from the columns of data units included in the block and input user control data. The data generation section generates the addresses and the sets of first parity symbols, required to generate the columns of data units included in the block, based on the initial address and the flag bytes, selects necessary portions from the flag bytes and the addresses and the sets of first parity symbols generated, and outputs the portions to the parity generation section, as the columns of data units included in the block.

摘要翻译： 编码器包括存储标志字节和初始地址的信息保持部分，从初始地址和标志字节产生第一奇偶校验符号集合的数据产生部分，生成并输出第二奇偶校验符号组的奇偶校验生成部分， 对于包括在块中的每列数据单元，包括在块中的数据单元的列和输入的用户控制数据。 数据生成部基于初始地址和标志字符生成基于该标志字节来生成包含在块中的数据单位列所需的第一奇偶校验符号的地址和集合，从标志字节和地址中选择必要部分， 生成的第一奇偶校验符号组，并将该部分输出到奇偶生成部分，作为包括在块中的数据单元的列。

公开(公告)号：US07831044B2

公开(公告)日：2010-11-09

申请号：US10579136

申请日：2004-11-10

申请人： Nobuyuki Yamamoto ,  Daigo Senoo

发明人： Nobuyuki Yamamoto ,  Daigo Senoo

IPC分类号： H04N7/169

CPC分类号： G11B20/00086 ,  G11B20/0021 ,  G11B20/00333 ,  G11B20/00347 ,  G11B20/00507

摘要： A data processing device of the invention has an ID creator unit (300) which adds ID information which is set by a CPU and the number of sectors, and outputs a result of the addition as ID information; a scramble SEED value table (103) which produces an initial scramble SEED value, by using the ID information which is outputted from the ID creator unit (300); a normal scramble filter (104) which produces a scramble SEED value (402) for data to be transferred; a frame jumping scramble filter (301) which holds a scramble SEED value of a jumping destination (401) in preparation for jumping; and a selector (105) which selects one of the scramble SEED value (401) and the scramble SEED value (402) and outputs the selected value to the normal scramble filter (104). Accordingly, the data processing device can perform a scrambling process and a de-scrambling process, without depending on the reliability of the data being transferred.

摘要翻译： 本发明的数据处理装置具有ID生成单元（300），其添加由CPU设定的ID信息和扇区数，并输出添加结果作为ID信息; 通过使用从ID创建单元（300）输出的ID信息产生初始加扰SEED值的加扰SEED值表（103）; 正常扰频滤波器（104），其产生用于要传送的数据的加扰SEED值（402）; 保持跳跃目的地（401）的加扰SEED值准备跳跃的帧跳跃加扰滤波器（301）; 以及选择器（105），其选择加密SEED值（401）和加密SEED值（402）中的一个，并将所选择的值输出到正常加扰滤波器（104）。 因此，数据处理装置可以执行加扰处理和去加扰处理，而不依赖于正在传送的数据的可靠性。

公开(公告)号：US20100287336A1

公开(公告)日：2010-11-11

申请号：US12843500

申请日：2010-07-26

申请人： Shinsuke TANAKA ,  Daigo SENOO

发明人： Shinsuke TANAKA ,  Daigo SENOO

IPC分类号： G06F12/08 ,  H03K19/177

CPC分类号： G11C11/406 ,  G11C11/40611

摘要： In an LSI that determines timing of DRAM refresh by a refresh timer to synchronize an external I/O signal and DRAM refresh timing with each other, a circuit configuration capable of controlling a value of the refresh timer by a CPU at arbitrary timing is employed. Alternatively, a circuit configuration capable of controlling the value of the refresh timer at arbitrary timing by an external terminal, or a circuit configuration capable of controlling the refresh timing directly from the external terminal without through the refresh timer.

摘要翻译： 在通过刷新定时器确定DRAM刷新的定时以使外部I / O信号和DRAM刷新时序相互同步的LSI中，采用能够以任意的时刻由CPU来控制刷新定时器的值的电路结构。 或者，能够通过外部端子在任意定时控制刷新定时器的值的电路配置，或者能够直接通过刷新定时器从外部终端控制刷新定时的电路配置。

公开(公告)号：US20100235719A1

公开(公告)日：2010-09-16

申请号：US12718490

申请日：2010-03-05

申请人： Daigo Senoo

发明人： Daigo Senoo

IPC分类号： H03M13/09 ,  H03M13/07 ,  G06F11/10

CPC分类号： H03M13/2954 ,  G11B20/1217 ,  G11B20/1833 ,  G11B20/1866 ,  G11B2020/1267 ,  G11B2020/1836 ,  G11B2020/1846 ,  G11B2220/2541 ,  H03M13/15 ,  H03M13/1515

摘要： An encoder includes an information holding section which stores flag bytes and an initial address, a data generation section which generates sets of first parity symbols from the initial address and the flag bytes, a parity generation section which generates and outputs sets of second parity symbols, for each column of data units included in the block, from the columns of data units included in the block and input user control data. The data generation section generates the addresses and the sets of first parity symbols, required to generate the columns of data units included in the block, based on the initial address and the flag bytes, selects necessary portions from the flag bytes and the addresses and the sets of first parity symbols generated, and outputs the portions to the parity generation section, as the columns of data units included in the block.

摘要翻译： 编码器包括存储标志字节和初始地址的信息保持部分，从初始地址和标志字节产生第一奇偶校验符号集合的数据产生部分，生成并输出第二奇偶校验符号组的奇偶校验生成部分， 对于包括在块中的每列数据单元，包括在块中的数据单元的列和输入的用户控制数据。 数据生成部基于初始地址和标志字符生成基于该标志字节来生成包含在块中的数据单位列所需的第一奇偶校验符号的地址和集合，从标志字节和地址中选择必要部分， 生成的第一奇偶校验符号组，并将该部分输出到奇偶生成部分，作为包括在块中的数据单元的列。

公开(公告)号：US20080152131A1

公开(公告)日：2008-06-26

申请号：US11905531

申请日：2007-10-02

申请人： Daigo SENOO

发明人： Daigo SENOO

IPC分类号： H04L9/18

CPC分类号： H04L25/03866

摘要： A data transfer device is provided for descrambling and deinterleaving scrambled interleaved data and transferring the resultant data. An interleave memory stores interleaved data in descrambling units. A DMA device outputs data position information indicating a storage position of each byte of the interleaved data stored in the interleave memory. A descrambling device receives data read out from each column of the interleave memory 13 in units of n bytes (n is a positive integer), and descrambles the data based on the data position information output from the DMA device.

摘要翻译： 提供数据传送装置，用于对加扰的交织数据进行解扰和解交织，并转送所得数据。 交织存储器以解扰单元存储交织数据。 DMA设备输出指示存储在交织存储器中的交织数据的每个字节的存储位置的数据位置信息。 解扰装置从n个字节（n为正整数）的单位接收从交错存储器13的各列读出的数据，并根据从DMA装置输出的数据位置信息进行解扰。

公开(公告)号：US20070266187A1

公开(公告)日：2007-11-15

申请号：US11663969

申请日：2005-09-05

申请人： Daigo Senoo

发明人： Daigo Senoo

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G11B20/10527 ,  G11B2020/1062 ,  G11B2020/10629 ,  G11B2020/10796 ,  G11B2220/2541 ,  H03M13/27

摘要： In a data interleaving apparatus, a SRAM sorting circuit 800 judges which the first half (SRAMs 700 and 710) or the latter half (SRAMs 720 and 730) of memory region SRAMs 700 through 730 address information for deinterleaving data transmitted by a DMA apparatus 100 corresponds to, and perform allocation. The DMA apparatus 100 transmits two addresses each time and data corresponding to one of the two addresses is written in a first memory region (SRAM 700 or 720) divided in a different manner from the above, and at the same time, data corresponding to the other one of the addresses is written in a second memory region (SRAM 710 or 730). In a DMA apparatus 200 for transmitting an address for taking out interleave data, a SRAM sorting circuit 810 performs, in the same manner, simultaneous processing to the first half and latter half regions in the memory SRAMs and simultaneous processing to the first and second memory regions. Accordingly, operation speed can be improved without increasing a frequency.

摘要翻译： 在数据交错装置中，SRAM分类电路800判断存储器区域SRAM 700至730的前半部分（SRAM 700和710）或后半部分（SRAM 720和730）是否存储由DMA装置100发送的数据进行解交织的信息 对应并执行分配。 DMA装置100每次发送两个地址，并且将与两个地址中的一个对应的数据写入与上述不同的方式分割的第一存储区域（SRAM700或720），同时，对应于 另一个地址被写入第二存储器区域（SRAM 710或730）。 在用于发送用于取出交错数据的地址的DMA装置200中，SRAM分类电路810以相同的方式执行对存储器SRAM中的前半个和后半个区域的同时处理以及对第一和第二存储器的同时处理 地区。 因此，可以在不增加频率的情况下提高操作速度。

公开(公告)号：US20100070720A1

公开(公告)日：2010-03-18

申请号：US12447320

申请日：2007-10-22

申请人： Yukikazu Kuramoto ,  Daigo Senoo

发明人： Yukikazu Kuramoto ,  Daigo Senoo

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0292 ,  G11C29/56 ,  G11C29/56004 ,  G11C2029/1806

摘要： The memory access method of the present invention comprises preparing upper addresses separately from the address width of the Pseudo SRAM (200) as virtual addresses at cutting out inspection patterns, and utilizing the Pseudo SRAM (200) as a test memory having the address width of the internal CPU (101). Then, while there are only actual addresses in the number which corresponds to the memory capacity, when the memory is accessed with exceeding the actual address value at the inspection, the actual address and virtual address are distinguished from each other based on the number of times of accesses.Thereby, the extension of addresses up to the number of addresses which are used in the internal CPU is performed to the maximum, and thereby the address insufficiency at using the real memory is solved.

摘要翻译： 本发明的存储器访问方法包括：在切断检查图案时，将伪地址（200）的地址宽度与伪地址宽度（200）分开制作，并利用伪SRAM（200）作为地址宽度为 内部CPU（101）。 然后，虽然只有与存储器容量相对应的数量中的实际地址，当在超过检查实际地址值的情况下访问存储器时，实际地址和虚拟地址基于次数来区分 的访问。 由此，最大限度地进行到内部CPU使用的地址数量的扩展，从而解决了使用真实存储器时的地址不足。

公开(公告)号：US20100027398A1

公开(公告)日：2010-02-04

申请号：US12519938

申请日：2007-12-20

申请人： Takahiro Ichikura ,  Hideo Sakon ,  Yorikazu Takao ,  Daigo Senoo ,  Youichi Ogura

发明人： Takahiro Ichikura ,  Hideo Sakon ,  Yorikazu Takao ,  Daigo Senoo ,  Youichi Ogura

IPC分类号： G11B7/00

CPC分类号： G11B7/00458 ,  G11B7/00454 ,  G11B7/0053 ,  G11B20/10009 ,  G11B20/10222 ,  G11B20/1403 ,  G11B2020/1274 ,  G11B2020/1287 ,  G11B2220/215 ,  G11B2220/2562

摘要： There is provided an optical disc device which can evaluate in a short time as to whether an optical disc is recorded with satisfying the standard or not.An optical disc device for measuring a recording deviation amount of data recorded on an optical disc on which physical addresses are previously provided, includes an address detection circuit which detects the physical address and outputs a physical address detection signal, a timer which is operated in synchronization with reproduced data from the optical disc, a recording deviation amount measurement circuit which measures the recording deviation amount of data recorded on the optical disc by using the physical address detection signal and the count value of the timer, a memory which stores the measured recording deviation amount, and a data transfer circuit which transfers the recording deviation amount to the memory.

摘要翻译： 提供了一种能够在短时间内评估光盘是否满足标准的光盘的光盘装置。 用于测量记录在预先提供了物理地址的光盘上的数据的记录偏差量的光盘装置包括检测物理地址并输出物理地址检测信号的地址检测电路，同步操作的定时器 来自光盘的再现数据，记录偏差量测量电路，其通过使用物理地址检测信号和计时器的计数值来测量记录在光盘上的数据的记录偏差量;存储器，其存储测量的记录偏差 以及将记录偏差量传送到存储器的数据传送电路。

公开(公告)号：US20090113269A1

公开(公告)日：2009-04-30

申请号：US12088126

申请日：2006-09-25

申请人： Daigo Senoo

发明人： Daigo Senoo

IPC分类号： H03M13/05 ,  G06F11/07

CPC分类号： H04L9/0866 ,  H04L9/0891 ,  H04L2209/34

摘要： When performing data descrambling for data including errors, a countermeasure against an error in a seed value that is required for the descrambling is realized in a system having no CPU.There are provided an FIFO unit (202) in which data are stored, an error correction unit (205) for receiving the data contents from the FIFO unit and performing error detection, an ID holding register (204) for holding a seed that is needed for data descrambling or information that is needed for seed generation when the data contents are judged as correct data as a result of the error detection by the error correction unit, and a descrambling unit (203) for receiving the data from the FIFO and performing descrambling by using the value stored in the ID holding register. Therefore, it is possible to perform data descrambling even in a situation where a CPU cannot manage the seed value because the transfer data are used.

摘要翻译： 当对包含错误的数据执行数据解扰时，在没有CPU的系统中实现针对解扰所需的种子值中的错误的对策。 提供存储数据的FIFO单元（202），用于从FIFO单元接收数据内容并执行错误检测的纠错单元（205），用于保存所需种子的ID保持寄存器（204） 作为由错误校正单元进行的错误检测的结果将数据内容判断为正确数据时，用于数据解扰或种子生成所需的信息，以及用于从FIFO接收数据并进行解扰的解扰单元（203） 通过使用存储在ID保持寄存器中的值。 因此，即使在使用传送数据的情况下CPU也无法管理种子值的情况下也可以进行数据解扰。