In a data interleaving apparatus, a SRAM sorting circuit 800 judges which the first half (SRAMs 700 and 710) or the latter half (SRAMs 720 and 730) of memory region SRAMs 700 through 730 address information for deinterleaving data transmitted by a DMA apparatus 100 corresponds to, and perform allocation. The DMA apparatus 100 transmits two addresses each time and data corresponding to one of the two addresses is written in a first memory region (SRAM 700 or 720) divided in a different manner from the above, and at the same time, data corresponding to the other one of the addresses is written in a second memory region (SRAM 710 or 730). In a DMA apparatus 200 for transmitting an address for taking out interleave data, a SRAM sorting circuit 810 performs, in the same manner, simultaneous processing to the first half and latter half regions in the memory SRAMs and simultaneous processing to the first and second memory regions. Accordingly, operation speed can be improved without increasing a frequency.