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1.发明授权公开(公告)号：US08242582B2
公开(公告)日：2012-08-14
申请号：US12647657
申请日：2009-12-28
申请人： Bok Gyu Min , Jae Myun Kim , Da Un Nah
发明人： Bok Gyu Min , Jae Myun Kim , Da Un Nah
IPC分类号： H01L23/00
CPC分类号： H01L23/3128 , H01L24/48 , H01L25/0657 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a semiconductor chip possessing a shape with corners and has a circuit section. The semiconductor chip has one or more chamfered portions which are formed in a first corner group that includes one or more of the corners. Data bonding pads are disposed on the semiconductor chip and are electrically connected to the circuit section. A chip selection pad is disposed adjacent to a second corner group that includes at least one of the corners which is not formed with a chamfered portion. The chip selection pad is electrically connected to the circuit section. A plurality of the semiconductor packages may be stacked so that the chip selection pad of one of the semiconductor packages is left exposed when another semiconductor package is stacked thereover due to the chamfered portion of the other semiconductor package.
摘要翻译： 半导体封装包括具有拐角形状并具有电路部分的半导体芯片。 半导体芯片具有形成在包括一个或多个拐角的第一角组中的一个或多个倒角部分。 数据接合焊盘设置在半导体芯片上并与电路部分电连接。 芯片选择焊盘被布置成与包括未形成有倒角部分的角部中的至少一个的第二角部组相邻。 芯片选择板电连接到电路部分。 可以堆叠多个半导体封装，使得当另一个半导体封装由于另一个半导体封装的倒角部分堆叠而使半导体封装中的一个的芯片选择焊盘露出。
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2.发明申请公开(公告)号：US20120032342A1
公开(公告)日：2012-02-09
申请号：US12981463
申请日：2010-12-29
申请人： Bok Gyu MIN , Joon Ki HONG , Tae Hoon KIM , Da Un NAH , Jae Joon AHN , Ki Bum KIM
发明人： Bok Gyu MIN , Joon Ki HONG , Tae Hoon KIM , Da Un NAH , Jae Joon AHN , Ki Bum KIM
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L2224/16 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/15311
摘要： A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type.
摘要翻译： 半导体封装包括：第一，第二，第三和第四半导体芯片，同时具有芯片选择通孔的布置; 以及连接单元，设置在第二半导体芯片和第三半导体芯片之间，并且被配置为相互连接第二和第三半导体芯片的一些芯片选择通孔，并且断开第二和第三半导体芯片的芯片选择通孔中的其它芯片 ，其中第一和第二半导体芯片以及第三和第四半导体芯片以倒装芯片类型堆叠。
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3.发明授权Selecting chips within a stacked semiconductor package using through-electrodes 有权使用贯通电极选择堆叠半导体封装内的芯片公开(公告)号：US08525319B2
公开(公告)日：2013-09-03
申请号：US12981443
申请日：2010-12-29
申请人： Bok Gyu Min , Kyoung Sook Park , Da Un Nah
发明人： Bok Gyu Min , Kyoung Sook Park , Da Un Nah
IPC分类号： H01L23/48
CPC分类号： H01L23/49827 , H01L23/481 , H01L23/49816 , H01L23/5382 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2224/48227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06572 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： A stacked semiconductor package includes first and second semiconductor chips including semiconductor chip bodies which have circuit units, first through-electrodes which pass through the semiconductor chip bodies at first positions, and second through-electrodes which pass through the semiconductor chip bodies at second positions and provide a chip enable signal to the circuit units. A spacer including a spacer body may be interposed between the first semiconductor chip and the second semiconductor chip, with an inverter chip embedded in the spacer body. Wiring patterns formed on the spacer body may connect the first through-electrodes of the first semiconductor chip with the second through-electrodes of the second semiconductor chip, the first through-electrodes of the first semiconductor chip with input terminals of the inverter chip, and output terminals of the inverter chip with the second through-electrodes of the first semiconductor chip.
摘要翻译： 堆叠半导体封装包括第一和第二半导体芯片，其包括具有电路单元的半导体芯片体，在第一位置穿过半导体芯片体的第一贯通电极以及在第二位置穿过半导体芯片体的第二贯通电极， 向电路单元提供芯片使能信号。 可以在第一半导体芯片和第二半导体芯片之间插入包括间隔体的间隔物，其中嵌入在间隔体中的逆变器芯片。 形成在间隔体上的接线图可以将第一半导体芯片的第一贯通电极与第二半导体芯片的第二贯通电极，第一半导体芯片的第一贯通电极与逆变器芯片的输入端子连接， 逆变器芯片的输出端子与第一半导体芯片的第二贯通电极。
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4.发明授权公开(公告)号：US08624375B2
公开(公告)日：2014-01-07
申请号：US12981463
申请日：2010-12-29
申请人： Bok Gyu Min , Joon Ki Hong , Tae Hoon Kim , Da Un Nah , Jae Joon Ahn , Ki Bum Kim
发明人： Bok Gyu Min , Joon Ki Hong , Tae Hoon Kim , Da Un Nah , Jae Joon Ahn , Ki Bum Kim
IPC分类号： H01L23/52
CPC分类号： H01L25/0657 , H01L2224/16 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/15311
摘要： A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type.
摘要翻译： 半导体封装包括：第一，第二，第三和第四半导体芯片，同时具有芯片选择通孔的布置; 以及连接单元，设置在第二半导体芯片和第三半导体芯片之间，并且被配置为相互连接第二和第三半导体芯片的一些芯片选择通孔，并且断开第二和第三半导体芯片的芯片选择通孔中的其它芯片 ，其中第一和第二半导体芯片以及第三和第四半导体芯片以倒装芯片类型堆叠。
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5.发明申请SPIRAL STAIRCASE SHAPED STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME 失效螺旋形平台堆叠式半导体封装及其制造方法公开(公告)号：US20110108995A1
公开(公告)日：2011-05-12
申请号：US12819279
申请日：2010-06-21
申请人： Da Un NAH , Jae Myun KIM , Tae Hoon KIM , Jung Tae JEONG , Bok Gyu MIN , Ki Bum KIM
发明人： Da Un NAH , Jae Myun KIM , Tae Hoon KIM , Jung Tae JEONG , Bok Gyu MIN , Ki Bum KIM
CPC分类号： H01L24/73 , H01L23/481 , H01L24/16 , H01L24/48 , H01L25/0657 , H01L2224/05554 , H01L2224/13025 , H01L2224/13099 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48108 , H01L2224/48227 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A spiral staircase shaped stacked semiconductor package is presented. The package includes a semiconductor chip module, a substrate and connection members. The semiconductor chip module includes at least two semiconductor chips which have chip selection pads and through-electrodes. The semiconductor chips are stacked such that the chip selection pads are exposed and the through-electrodes of the stacked semiconductor chips are electrically connected to one another. The substrate has the semiconductor chip module mounted thereto and has connection pads. The connection members electrically connect the chip selection pads to respective connection pads.
摘要翻译： 提出了一种螺旋状梯形堆叠半导体封装。 封装包括半导体芯片模块，基板和连接构件。 半导体芯片模块包括具有芯片选择焊盘和贯通电极的至少两个半导体芯片。 堆叠半导体芯片，使得芯片选择焊盘被暴露，并且堆叠的半导体芯片的贯通电极彼此电连接。 基板具有安装在其上的半导体芯片模块并具有连接焊盘。 连接构件将芯片选择焊盘电连接到相应的连接焊盘。
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公开(公告)号：US20110031591A1
公开(公告)日：2011-02-10
申请号：US12647657
申请日：2009-12-28
申请人： Bok Gyu MIN , Jae Myun KIM , Da Un NAH
发明人： Bok Gyu MIN , Jae Myun KIM , Da Un NAH
IPC分类号： H01L23/00
CPC分类号： H01L23/3128 , H01L24/48 , H01L25/0657 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a semiconductor chip possessing a shape with corners and has a circuit section. The semiconductor chip has one or more chamfered portions which are formed in a first corner group that includes one or more of the corners. Data bonding pads are disposed on the semiconductor chip and are electrically connected to the circuit section. A chip selection pad is disposed adjacent to a second corner group that includes at least one of the corners which is not formed with a chamfered portion. The chip selection pad is electrically connected to the circuit section. A plurality of the semiconductor packages may be stacked so that the chip selection pad of one of the semiconductor packages is left exposed when another semiconductor package is stacked thereover due to the chamfered portion of the other semiconductor package.
摘要翻译： 半导体封装包括具有拐角形状并具有电路部分的半导体芯片。 半导体芯片具有形成在包括一个或多个拐角的第一角组中的一个或多个倒角部分。 数据接合焊盘设置在半导体芯片上并与电路部分电连接。 芯片选择焊盘被布置成与包括未形成有倒角部分的角部中的至少一个的第二角部组相邻。 芯片选择板电连接到电路部分。 可以堆叠多个半导体封装，使得当另一个半导体封装由于另一个半导体封装的倒角部分堆叠而使半导体封装中的一个的芯片选择焊盘露出。
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7.发明授权Spiral staircase shaped stacked semiconductor package and method for manufacturing the same 失效螺旋状楼梯状叠层半导体封装及其制造方法公开(公告)号：US08304879B2
公开(公告)日：2012-11-06
申请号：US12819279
申请日：2010-06-21
申请人： Da Un Nah , Jae Myun Kim , Tae Hoon Kim , Jung Tae Jeong , Bok Gyu Min , Ki Bum Kim
发明人： Da Un Nah , Jae Myun Kim , Tae Hoon Kim , Jung Tae Jeong , Bok Gyu Min , Ki Bum Kim
IPC分类号： H01L23/482
CPC分类号： H01L24/73 , H01L23/481 , H01L24/16 , H01L24/48 , H01L25/0657 , H01L2224/05554 , H01L2224/13025 , H01L2224/13099 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48108 , H01L2224/48227 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A spiral staircase shaped stacked semiconductor package is presented. The package includes a semiconductor chip module, a substrate and connection members. The semiconductor chip module includes at least two semiconductor chips which have chip selection pads and through-electrodes. The semiconductor chips are stacked such that the chip selection pads are exposed and the through-electrodes of the stacked semiconductor chips are electrically connected to one another. The substrate has the semiconductor chip module mounted thereto and has connection pads. The connection members electrically connect the chip selection pads to respective connection pads.
摘要翻译： 提出了一种螺旋状梯形堆叠半导体封装。 封装包括半导体芯片模块，基板和连接构件。 半导体芯片模块包括具有芯片选择焊盘和贯通电极的至少两个半导体芯片。 堆叠半导体芯片，使得芯片选择焊盘被暴露，并且堆叠的半导体芯片的贯通电极彼此电连接。 基板具有安装在其上的半导体芯片模块并具有连接焊盘。 连接构件将芯片选择焊盘电连接到相应的连接焊盘。
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8.发明申请SELECTING CHIPS WITHIN A STACKED SEMICONDUCTOR PACKAGE USING THROUGH-ELECTRODES 有权在使用电极的堆叠半导体封装中选择晶片公开(公告)号：US20110272804A1
公开(公告)日：2011-11-10
申请号：US12981443
申请日：2010-12-29
申请人： Bok Gyu MIN , Kyoung Sook PARK , Da Un NAH
发明人： Bok Gyu MIN , Kyoung Sook PARK , Da Un NAH
IPC分类号： H01L23/48
CPC分类号： H01L23/49827 , H01L23/481 , H01L23/49816 , H01L23/5382 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2224/48227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06572 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： A stacked semiconductor package includes first and second semiconductor chips including semiconductor chip bodies which have circuit units, first through-electrodes which pass through the semiconductor chip bodies at first positions, and second through-electrodes which pass through the semiconductor chip bodies at second positions and provide a chip enable signal to the circuit units. A spacer including a spacer body may be interposed between the first semiconductor chip and the second semiconductor chip, with an inverter chip embedded in the spacer body. Wiring patterns formed on the spacer body may connect the first through-electrodes of the first semiconductor chip with the second through-electrodes of the second semiconductor chip, the first through-electrodes of the first semiconductor chip with input terminals of the inverter chip, and output terminals of the inverter chip with the second through-electrodes of the first semiconductor chip.
摘要翻译： 堆叠半导体封装包括第一和第二半导体芯片，其包括具有电路单元的半导体芯片体，在第一位置穿过半导体芯片体的第一贯通电极以及在第二位置穿过半导体芯片体的第二贯通电极， 向电路单元提供芯片使能信号。 可以在第一半导体芯片和第二半导体芯片之间插入包括间隔体的间隔物，其中嵌入在间隔体中的逆变器芯片。 形成在间隔体上的接线图可以将第一半导体芯片的第一贯通电极与第二半导体芯片的第二贯通电极，第一半导体芯片的第一贯通电极与逆变器芯片的输入端子连接， 逆变器芯片的输出端子与第一半导体芯片的第二贯通电极。
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