知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

105 条记录 (耗时 0.033 秒)

    Scheduler pipeline design for hierarchical link sharing
    5.
    发明授权
    Scheduler pipeline design for hierarchical link sharing 失效
    调度器管道设计用于分层链路共享

    公开(公告)号：US07929438B2

    公开(公告)日：2011-04-19

    申请号：US12175479

    申请日：2008-07-18

    申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

    发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

    IPC分类号： H04J1/16

    CPC分类号： H04L47/60 ,  H04L47/15 ,  H04L47/50 ,  H04L47/52 ,  H04L49/90

    摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.

    摘要翻译： 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。