公开(公告)号：US08515489B2

公开(公告)日：2013-08-20

申请号：US13220026

申请日：2011-08-29

申请人： Yi-Ting Chang ,  Chih-Yung Shih ,  Chen-Wei Hsu ,  Chia-Yi Huang ,  Chung-Cheng Yu

发明人： Yi-Ting Chang ,  Chih-Yung Shih ,  Chen-Wei Hsu ,  Chia-Yi Huang ,  Chung-Cheng Yu

IPC分类号： H04M1/00

CPC分类号： H04W72/1215 ,  H04W88/06

摘要： A communications apparatus with a processor coupled to a first RAT module in a packet transfer mode for data transfer, a second RAT module in an idle mode and a radio transceiver are provided. The processor receives a reservation request requesting permission to use the radio transceiver for performing a first radio activity from the first RAT module, and determines whether to provide a gap interval during the data transfer of the second RAT module for the first RAT module to use the radio transceiver according to a type of a second radio activity to be preformed by the second RAT module which collides with the first radio activity. When the gap interval is determined to be provided, the second RAT module is unable to use the radio transceiver for performing the second radio activity and the data transfer of the second RAT module is suspended during the gap interval.

摘要翻译： 一种具有处理器的处理器，其以用于数据传输的分组传送模式耦合到第一RAT模块，提供处于空闲模式的第二RAT模块和无线电收发器。 处理器接收请求许可的预留请求，以使用无线电收发器来执行来自第一RAT模块的第一无线电活动，并且确定是否在第一RAT模块的第二RAT模块的数据传输期间提供间隙间隔以使用 无线电收发器根据要与第一无线电活动相冲突的第二RAT模块执行的第二无线电活动的类型。 当确定提供间隙间隔时，第二RAT模块不能使用无线电收发器来执行第二无线电活动，并且在间隙间隔期间暂停第二RAT模块的数据传输。

公开(公告)号：US20130053076A1

公开(公告)日：2013-02-28

申请号：US13220026

申请日：2011-08-29

申请人： Yi-Ting Chang ,  Chih-Yung Shih ,  Chen-Wei Hsu ,  Chia-Yi Huang ,  Chung-Cheng Yu

发明人： Yi-Ting Chang ,  Chih-Yung Shih ,  Chen-Wei Hsu ,  Chia-Yi Huang ,  Chung-Cheng Yu

IPC分类号： H04W72/04

CPC分类号： H04W72/1215 ,  H04W88/06

摘要： A communications apparatus with a processor coupled to a first RAT module in a packet transfer mode for data transfer, a second RAT module in an idle mode and a radio transceiver are provided. The processor receives a reservation request requesting permission to use the radio transceiver for performing a first radio activity from the first RAT module, and determines whether to provide a gap interval during the data transfer of the second RAT module for the first RAT module to use the radio transceiver according to a type of a second radio activity to be preformed by the second RAT module which collides with the first radio activity. When the gap interval is determined to be provided, the second RAT module is unable to use the radio transceiver for performing the second radio activity and the data transfer of the second RAT module is suspended during the gap interval.

摘要翻译： 一种具有处理器的处理器，其以用于数据传输的分组传送模式耦合到第一RAT模块，提供处于空闲模式的第二RAT模块和无线电收发器。 处理器接收请求许可的预留请求，以使用无线电收发器来执行来自第一RAT模块的第一无线电活动，并且确定是否在第一RAT模块的第二RAT模块的数据传输期间提供间隙间隔以使用 无线电收发器根据要与第一无线电活动相冲突的第二RAT模块执行的第二无线电活动的类型。 当确定提供间隙间隔时，第二RAT模块不能使用无线电收发器来执行第二无线电活动，并且在间隙间隔期间暂停第二RAT模块的数据传输。

公开(公告)号：US08165188B2

公开(公告)日：2012-04-24

申请号：US12346897

申请日：2008-12-31

申请人： Chih-Yung Shih ,  Liang-Wei Huang ,  Shieh-Hsing Kuo ,  Chi-Shun Weng

发明人： Chih-Yung Shih ,  Liang-Wei Huang ,  Shieh-Hsing Kuo ,  Chi-Shun Weng

IPC分类号： H04L5/16

CPC分类号： H04L7/033 ,  H03L7/0812 ,  H04B3/23 ,  H04L7/0087

摘要： A transceiver includes: a first DAC, for receiving a first digital signal to generate an analog signal; an operation circuit, coupled to the first DAC, for receiving the analog signal and a feedback signal to generate an operated analog signal; an ADC, for generating a second digital signal according to the operated analog signal; a digital signal processing circuit, for processing the second digital signal to generate a processed digital signal; a second DAC, for generating the feedback signal according to the processed digital signal; an adjustable delay circuit, for delaying a clock signal according to a control signal to adjust at least one sampling point of at least one of the first DAC, the second DAC and the ADC; and a control circuit, for generating the control signal according to the processed digital signal.

摘要翻译： 收发器包括：第一DAC，用于接收第一数字信号以产生模拟信号; 耦合到第一DAC的操作电路，用于接收模拟信号和反馈信号以产生操作的模拟信号; ADC，用于根据所操作的模拟信号产生第二数字信号; 数字信号处理电路，用于处理第二数字信号以产生经处理的数字信号; 第二DAC，用于根据所处理的数字信号产生反馈信号; 可调延迟电路，用于根据控制信号延迟时钟信号以调整第一DAC，第二DAC和ADC中的至少一个的至少一个采样点; 以及控制电路，用于根据处理的数字信号产生控制信号。

公开(公告)号：US08108334B2

公开(公告)日：2012-01-31

申请号：US12022449

申请日：2008-01-30

申请人： Chih-Yung Shih

发明人： Chih-Yung Shih

IPC分类号： G06F15/00 ,  G06F15/18 ,  G06F15/16 ,  G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00

CPC分类号： G06F7/22 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/658 ,  H03M13/6583

摘要： The present invention relates to a search circuit in a decoding unit of low-density parity-check codes, which used for searching a minimum value and a next minimum value from r input values, where r is an integer greater than 3. The search circuit includes a first search circuit and a second search circuit. The search method includes performing operations on each pair of input values Vi, Vj of the r input values, respectively. The second search circuit, which is coupled to the first search circuit, performs operations on every two sets of compared values Wm, Lm, and Wn, Ln of the s compared values, where s is a positive integer smaller than r, the smaller value Wm is smaller than the greater value Lm, and the smaller value Wn is smaller than the greater value Ln. The second search circuit performs operations according to the smaller value Wo and the greater value Lo to produce the minimum value and the next minimum value. Thereby, the search of the minimum value, the next minimum value, and the address of the minimum value can be performed at the same time without the need of waiting completion of search for the minimum value then the next minimum value can be searched.

摘要翻译： 本发明涉及低密度奇偶校验码的解码单元中的搜索电路，其用于从r个输入值搜索最小值和下一个最小值，其中r是大于3的整数。搜索电路 包括第一搜索电路和第二搜索电路。 搜索方法包括分别对r个输入值的每对输入值Vi，Vj执行操作。 耦合到第一搜索电路的第二搜索电路对s比较值的每两组比较值Wm，Lm和Wn，Ln进行操作，其中s是小于r的正整数，较小值 Wm小于较大值Lm，并且较小值Wn小于较大值Ln。 第二搜索电路根据较小的值Wo和较大的值Lo执行操作以产生最小值和下一个最小值。 因此，可以同时执行最小值，下一个最小值和最小值的地址的搜索，而不需要等待完成对最小值的搜索，然后可以搜索下一个最小值。

公开(公告)号：US07898992B2

公开(公告)日：2011-03-01

申请号：US12260101

申请日：2008-10-29

申请人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

发明人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

IPC分类号： H04B3/20 ,  H04B1/38 ,  H04L12/66

CPC分类号： H04B3/32 ,  H04B3/23 ,  H04L49/10

摘要： A network apparatus with a plurality of transport ports and a shared coefficient update processor is proposed. Each of the plurality of transport ports includes a PHY module. The coefficient update processor is coupled to each PHY module and is shared by the plurality of transport ports. The coefficient update processor decides coefficients of each PHY module. The coefficient update processor is dedicated to one of the plurality of transport ports for use in a period of time.

摘要翻译： 提出了具有多个传输端口和共享系数更新处理器的网络设备。 多个传输端口中的每一个包括PHY模块。 系数更新处理器耦合到每个PHY模块并由多个传输端口共享。 系数更新处理器决定每个PHY模块的系数。 系数更新处理器专用于多个传输端口中的一个，用于一段时间。

公开(公告)号：US20090225912A1

公开(公告)日：2009-09-10

申请号：US12398186

申请日：2009-03-05

申请人： Chih-Yung Shih ,  Liang-Wei Huang ,  Shieh-Hsing Kuo

发明人： Chih-Yung Shih ,  Liang-Wei Huang ,  Shieh-Hsing Kuo

IPC分类号： H03D1/04

CPC分类号： H04B3/23 ,  H04L2025/03617

摘要： A receiver for echo and crosstalk cancellation includes a level decision module, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC) and a response module. The level decision module determines plural levels and plural level magnitudes according to an estimated signal to generate a first digital signal. The DAC converts the first digital signal into a first analog signal according to the levels and the level magnitudes. The ADC receives a first difference signal between the receiving signal and the first analog signal, and converts the first difference signal into a second digital signal. According to the first digital signal, the response module generates a response signal compensating the second digital signal to generate a back-end input signal.

摘要翻译： 用于回波和串扰消除的接收器包括电平决定模块，数模转换器（DAC），模数转换器（ADC）和响应模块。 电平决定模块根据估计信号确定多个电平和多个电平大小以产生第一数字信号。 DAC根据电平和电平大小将第一数字信号转换为第一模拟信号。 ADC在接收信号和第一模拟信号之间接收第一差分信号，并将第一差分信号转换为第二数字信号。 根据第一数字信号，响应模块产生补偿第二数字信号的响应信号以产生后端输入信号。

公开(公告)号：US20090175322A1

公开(公告)日：2009-07-09

申请号：US12346897

申请日：2008-12-31

申请人： Chih-Yung Shih ,  Liang-Wei Huang ,  Shieh-Hsing Kuo ,  Chi-Shun Weng

发明人： Chih-Yung Shih ,  Liang-Wei Huang ,  Shieh-Hsing Kuo ,  Chi-Shun Weng

IPC分类号： H04B1/38

CPC分类号： H04L7/033 ,  H03L7/0812 ,  H04B3/23 ,  H04L7/0087

摘要： A transceiver includes: a first DAC, for receiving a first digital signal to generate an analog signal; an operation circuit, coupled to the first DAC, for receiving the analog signal and a feedback signal to generate an operated analog signal; an ADC, for generating a second digital signal according to the operated analog signal; a digital signal processing circuit, for processing the second digital signal to generate a processed digital signal; a second DAC, for generating the feedback signal according to the processed digital signal; an adjustable delay circuit, for delaying a clock signal according to a control signal to adjust at least one sampling point of at least one of the first DAC, the second DAC and the ADC; and a control circuit, for generating the control signal according to the processed digital signal.

摘要翻译： 收发器包括：第一DAC，用于接收第一数字信号以产生模拟信号; 耦合到第一DAC的操作电路，用于接收模拟信号和反馈信号，以产生操作的模拟信号; ADC，用于根据所操作的模拟信号产生第二数字信号; 数字信号处理电路，用于处理第二数字信号以产生经处理的数字信号; 第二DAC，用于根据所处理的数字信号产生反馈信号; 可调延迟电路，用于根据控制信号延迟时钟信号以调整第一DAC，第二DAC和ADC中的至少一个的至少一个采样点; 以及控制电路，用于根据处理的数字信号产生控制信号。

公开(公告)号：US09252994B2

公开(公告)日：2016-02-02

申请号：US12260099

申请日：2008-10-29

申请人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

发明人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

IPC分类号： H04J3/06 ,  H04L25/14 ,  H04L7/00 ,  H04L25/03

CPC分类号： H04L25/14 ,  H04J3/0685 ,  H04L7/0029 ,  H04L7/0079 ,  H04L2025/03369 ,  H04L2025/03477

摘要： A network apparatus, for processing a network signal and outputting an output signal, includes an asynchronous signal processing module, a sampling rate converter and a synchronous signal processing module. The asynchronous signal processing module operates in an asynchronous domain, and is utilized for receiving and processing the network signal to generate a first processed signal. The sampling rate converter is coupled to the asynchronous signal processing module, and is utilized for performing sampling rate conversion on the first processed signal to generate the output signal. A first operating frequency of the asynchronous signal processing module is different from a second operating frequency of the synchronous signal processing module.

摘要翻译： 用于处理网络信号并输出​​输出信号的网络装置包括异步信号处理模块，采样率转换器和同步信号处理模块。 异步信号处理模块在异步域中操作，并用于接收和处理网络信号以产生第一处理信号。 采样率转换器耦合到异步信号处理模块，并用于对第一处理信号进行采样率转换以产生输出信号。 异步信号处理模块的第一工作频率与同步信号处理模块的第二工作频率不同。

公开(公告)号：US09112265B2

公开(公告)日：2015-08-18

申请号：US13609090

申请日：2012-09-10

申请人： Tzuh-Suan Wang ,  Yu-Fu Kuo ,  Yuan-Chin Hsu ,  Chih-Yung Shih

发明人： Tzuh-Suan Wang ,  Yu-Fu Kuo ,  Yuan-Chin Hsu ,  Chih-Yung Shih

IPC分类号： H01P11/00 ,  H01Q1/24 ,  H01Q1/38

CPC分类号： H01Q1/243 ,  H01Q1/38 ,  Y10T29/49016

摘要： A method for manufacturing an antenna structure is disclosed. Employing steps of mixing with a catalyst and embedding a metal insert can simplify steps for manufacturing the antenna structure. Further, a non-conductive frame produced by the process disclosed herein can exhibit waterproof effect. The catalyst mentioned above is mixed with a plastic and then injected into a mold to form the non-conductive frame. The metal insert mentioned above is disposed in the mold before the step of injecting the plastic. Alternatively, the metal insert is embedded in the non-conductive frame after the step of injecting the plastic.

摘要翻译： 公开了一种用于制造天线结构的方法。 采用与催化剂混合并嵌入金属插入物的步骤可以简化制造天线结构的步骤。 此外，通过本文公开的方法制造的非导电框架可以表现出防水效果。 将上述催化剂与塑料混合，然后注入模具以形成非导电性框架。 上述金属插入件在注射塑料的步骤之前设置在模具中。 或者，在注塑塑料的步骤之后，将金属插入件嵌入非导电框架中。

公开(公告)号：US20130252614A1

公开(公告)日：2013-09-26

申请号：US13604375

申请日：2012-09-05

申请人： Ming-Wan HSU ,  Chung-Yun CHANG ,  Chang-Hua YANG ,  Chih-Chung LIN ,  Chien-Nan CHOU ,  Chih-Yung SHIH

发明人： Ming-Wan HSU ,  Chung-Yun CHANG ,  Chang-Hua YANG ,  Chih-Chung LIN ,  Chien-Nan CHOU ,  Chih-Yung SHIH

IPC分类号： H04W36/14

CPC分类号： H04W36/00835 ,  H04W36/14

摘要： A communications apparatus includes a processor coupled to at least one RF transceiver and at least one baseband processing device and capable of communicating with a first wireless network belonging to a first RAT and a second wireless network belonging to a second RAT having a higher data transmission throughput than the first RAT. A first processor logic unit of the processor performs an enhanced cell search procedure via the RF transceiver to find one or more cell(s) belonging to the second RAT having stronger signal strength and/or better signal quality than a predetermined threshold, which are not included in a broadcast neighbor cell list. A second processor logic unit of the processor determines a suitable cell from among the cell(s) and performs a cell reselection procedure to camp on the suitable cell.

摘要翻译： 通信设备包括处理器，其耦合到至少一个RF收发器和至少一个基带处理设备，并且能够与属于具有较高数据传输吞吐量的属于第一RAT的第一无线网络和属于第二RAT的第二无线网络进行通信 比第一RAT。 处理器的第一处理器逻辑单元经由RF收发器执行增强的小区搜索过程，以发现属于第二RAT的一个或多个小区具有比预定阈值更强的信号强度和/或更好的信号质量，其不是 包括在广播相邻小区列表中。 处理器的第二处理器逻辑单元从小区中确定合适的小区，并且执行小区重选过程来驻留在合适的小区上。