公开(公告)号：US08592321B2

公开(公告)日：2013-11-26

申请号：US13156319

申请日：2011-06-08

Applicant: Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

Inventor： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

IPC: H01L21/46 ,  H01L21/302

CPC classification number: H01L21/308 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816

Abstract: A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask.

Abstract translation: 公开了一种制造孔的方法。 该方法包括以下步骤：在半导体衬底的表面上形成含有碳的硬掩模; 并且使用含有气体的非氧元素进行用于在硬掩模中形成第一孔的第一蚀刻工艺。

公开(公告)号：US08252650B1

公开(公告)日：2012-08-28

申请号：US13092151

申请日：2011-04-22

Applicant: Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

Inventor： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

IPC: H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823864

Abstract: A method for fabricating MOS transistor includes the steps of: overlapping a second stress layer on an etching stop layer and a first stress layer at a boundary region of the substrate; forming a dielectric layer on the first stress layer and the second stress layer; performing a first etching process to partially remove the dielectric layer for exposing a portion of the second stress layer at the boundary region; performing a second etching process to partially remove the exposed portion of the second stress layer for exposing the etching stop layer; performing a third etching process to partially remove the exposed portion of the etching stop layer for exposing the first stress layer at the boundary region; and performing a fourth etching process partially remove the exposed portion of the first stress layer.

Abstract translation: 一种用于制造MOS晶体管的方法包括以下步骤：在蚀刻停止层和基板的边界区域处的第一应力层上重叠第二应力层; 在所述第一应力层和所述第二应力层上形成介电层; 执行第一蚀刻工艺以部分去除所述电介质层以暴露所述边界区域处的所述第二应力层的一部分; 执行第二蚀刻工艺以部分地去除第二应力层的暴露部分以暴露蚀刻停止层; 执行第三蚀刻工艺以部分地去除用于在边界区域露出第一应力层的蚀刻停止层的暴露部分; 并且执行第四蚀刻工艺部分地去除第一应力层的暴露部分。

公开(公告)号：US08592322B2

公开(公告)日：2013-11-26

申请号：US13535370

申请日：2012-06-28

Applicant: Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

Inventor： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

IPC: H01L21/302

CPC classification number: H01L21/76802 ,  H01L21/76831 ,  H01L21/76897

Abstract: A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.

Abstract translation: 公开了一种制造开口的方法。 首先，提供其上具有自对准硅化物区域的半导体衬底。 蚀刻停止层和至少介电层从底部到顶部设置在半导体衬底上。 其次，对电介质层和蚀刻停止层进行图案化以在电介质层和蚀刻停止层中形成多个开口，使得开口露出自对准区域。 然后，形成覆盖电介质层的电介质薄膜，开口侧壁和自对准硅化物区域。 然后，去除设置在电介质层和自对准硅化物区域上的电介质薄膜。

公开(公告)号：US08461649B2

公开(公告)日：2013-06-11

申请号：US13234159

申请日：2011-09-16

Applicant: Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

Inventor： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC: H01L29/78

CPC classification number: H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/485

Abstract: An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.

Abstract translation: 公开了一种开口结构。 开口结构包括：半导体衬底; 设置在所述半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁; 覆盖每个开口的侧壁的至少一部分的电介质薄膜; 蚀刻停止层，设置在所述半导体衬底和所述电介质层之间并且部分地延伸到所述开口中以将所述电介质薄膜与所述半导体衬底隔离; 以及填充在开口中的金属层。

公开(公告)号：US20120270403A1

公开(公告)日：2012-10-25

申请号：US13535370

申请日：2012-06-28

Applicant: Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

Inventor： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

IPC: H01L21/306

CPC classification number: H01L21/76802 ,  H01L21/76831 ,  H01L21/76897

Abstract: A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.

Abstract translation: 公开了一种制造开口的方法。 首先，提供其上具有自对准硅化物区域的半导体衬底。 蚀刻停止层和至少介电层从底部到顶部设置在半导体衬底上。 其次，对电介质层和蚀刻停止层进行图案化以在电介质层和蚀刻停止层中形成多个开口，使得开口露出自对准区域。 然后，形成覆盖电介质层的电介质薄膜，开口侧壁和自对准硅化物区域。 然后，去除设置在电介质层和自对准硅化物区域上的电介质薄膜。

公开(公告)号：US08293639B2

公开(公告)日：2012-10-23

申请号：US12371809

申请日：2009-02-16

Applicant: Feng-Yih Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

Inventor： Feng-Yih Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC: H01L21/4763

CPC classification number: H01L21/76804 ,  H01L21/31144 ,  H01L21/76895

Abstract: A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.

Abstract translation: 描述了用于控制具有不同尺寸的开口的ADI-AEI CD差异比率的方法。 开口依次形成为含硅材料层，蚀刻电阻层和靶材料层。 在开口蚀刻步骤之前，光致抗蚀剂掩模中的至少一个开口图案的尺寸通过基本上保形的聚合物层的光致抗蚀剂修饰或沉积而改变。 执行在更宽的开口图案的侧壁上形成较厚聚合物的第一蚀刻步骤以形成图案化的含Si材料层。 执行第二蚀刻步骤以去除蚀刻电阻层和目标材料层的暴露部分。 控制光致抗蚀剂修整或聚合物层沉积步骤的参数中的至少一个参数和第一蚀刻步骤的蚀刻参数以获得预定的ADI-AEI CD差异比。

公开(公告)号：US08164141B2

公开(公告)日：2012-04-24

申请号：US12884198

申请日：2010-09-17

Applicant: Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

Inventor： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC: H01L29/78

CPC classification number: H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/485

Abstract: An opening structure includes a semiconductor substrate, at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall, a dielectric thin film covering at least a portion of the sidewall of each of the openings, and a metal layer filled in the openings.

Abstract translation: 开口结构包括半导体衬底，设置在半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁，至少覆盖至少一个的电介质薄膜 每个开口的侧壁的一部分，以及填充在开口中的金属层。

公开(公告)号：US08101092B2

公开(公告)日：2012-01-24

申请号：US11877918

申请日：2007-10-24

Applicant: Chih-Wen Feng ,  Pei-Yu Chou ,  Chun-Ting Yeh ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Ying-Chih Lin

Inventor： Chih-Wen Feng ,  Pei-Yu Chou ,  Chun-Ting Yeh ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Ying-Chih Lin

IPC: C03C15/00 ,  H01L21/4763

CPC classification number: H01L21/31144 ,  H01L21/0276 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method for controlling ADI-AEI CD difference ratios of openings having different sizes is provided. First, a first etching step using a patterned photoresist layer as a mask is performed to form a patterned Si-containing material layer and a polymer layer on sidewalls thereof. Next, a second etching step is performed with the patterned photoresist layer, the patterned Si-containing material layer and the polymer layer as masks to at least remove an exposed portion of a etching resistive layer to form a patterned etching resistive layer. A portion of a target material layer is removed by using the patterned etching resistive layer as an etching mask to form a first and a second openings in the target material layer. The method is characterized by controlling etching parameters of the first and second etching steps to obtain predetermined ADI-AEI CD difference ratios.

Abstract translation: 提供了一种用于控制具有不同尺寸的开口的ADI-AEI CD差异比率的方法。 首先，使用图案化的光致抗蚀剂层作为掩模进行第一蚀刻步骤，以在其侧壁上形成图案化的含Si材料层和聚合物层。 接下来，利用图案化的光致抗蚀剂层，图案化的含Si材料层和聚合物层作为掩模来执行第二蚀刻步骤，以至少去除蚀刻电阻层的暴露部分以形成图案化的蚀刻电阻层。 通过使用图案化的蚀刻电阻层作为蚀刻掩模来去除目标材料层的一部分，以在靶材料层中形成第一和第二开口。 该方法的特征在于控制第一和第二蚀刻步骤的蚀刻参数以获得预定的ADI-AEI CD差异比。

公开(公告)号：US20120001338A1

公开(公告)日：2012-01-05

申请号：US13234159

申请日：2011-09-16

Applicant: Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

Inventor： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC: H01L23/48

CPC classification number: H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/485

Abstract: An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.

Abstract translation: 公开了一种开口结构。 开口结构包括：半导体衬底; 设置在所述半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁; 覆盖每个开口的侧壁的至少一部分的电介质薄膜; 蚀刻停止层，设置在所述半导体衬底和所述电介质层之间并且部分地延伸到所述开口中以将所述电介质薄膜与所述半导体衬底隔离; 以及填充在开口中的金属层。

公开(公告)号：US20110174774A1

公开(公告)日：2011-07-21

申请号：US12690935

申请日：2010-01-21

Applicant: Ying-Chih Lin ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Feng-Yi Chang ,  Shang-Yuan Tsai

Inventor： Ying-Chih Lin ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Feng-Yi Chang ,  Shang-Yuan Tsai

IPC: B44C1/22

CPC classification number: H01L21/0273 ,  G03F7/40 ,  H01L21/31138 ,  H01L21/31144

Abstract: A method of descumming a patterned photoresist is provided. First a material layer to be etched is provided. The material layer is covered by a patterned photoresist. Then a descum process is preformed to descum the edge of the patterned photoresist by nitrogen. Finally, the descummed patterned photoresist is used as a mask for etching the material layer.

Abstract translation: 提供了一种去除图案化光致抗蚀剂的方法。 首先提供待蚀刻的材料层。 材料层被图案化的光致抗蚀剂覆盖。 然后进行除氧过程以通过氮气除去图案化的光致抗蚀剂的边缘。 最后，将除去图案化的光致抗蚀剂用作蚀刻材料层的掩模。