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    Camera lens assembly
    1.
    发明授权
    Camera lens assembly 失效
    相机镜头组件

    公开(公告)号：US06898030B1

    公开(公告)日：2005-05-24

    申请号：US10868826

    申请日：2004-06-17

    Applicant: Jui-Hsin Lin ,  Ching-Pin Hsu

    Inventor： Jui-Hsin Lin ,  Ching-Pin Hsu

    IPC: G02B7/00 ,  G02B7/02

    CPC classification number: G02B7/021 ,  G02B7/006

    Abstract: A camera lens includes a barrel, a first lens, a second lens and an optical filter module. The barrel includes a first container and a diaphragm. The first lens is disposed in the first container next to the diaphragm. The second lens is disposed in the first container with a distance from the first lens. The optical filter module is disposed in the first container between the first and the second lenses.

    Abstract translation: 相机镜头包括镜筒，第一透镜，第二透镜和滤光器模块。 桶包括第一容器和隔膜。 第一透镜设置在隔膜旁边的第一容器中。 第二透镜设置在与第一透镜相距一定距离的第一容器中。 滤光器模块设置在第一和第二透镜之间的第一容器中。

    METHOD FOR FORMING VOID-FREE DIELECTRIC LAYER
    2.
    发明申请
    METHOD FOR FORMING VOID-FREE DIELECTRIC LAYER 有权
    形成无电介质层的方法

    公开(公告)号：US20130109151A1

    公开(公告)日：2013-05-02

    申请号：US13281459

    申请日：2011-10-26

    Applicant: Ching-Pin Hsu ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Shang-Yuan Tsai ,  Li-Chiang Chen

    Inventor： Ching-Pin Hsu ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Shang-Yuan Tsai ,  Li-Chiang Chen

    IPC: H01L21/762

    CPC classification number: H01L21/76232

    Abstract: A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.

    Abstract translation: 公开了一种形成没有空隙的电介质层的方法。 首先，提供基板，包括凹部的第一应力层，设置在第一应力层上并覆盖凹部的第二应力层和嵌入凹部中的图案化光致抗蚀剂。 第二，执行第一蚀刻步骤以完全去除光致抗蚀剂，使得剩余的第二应力层形成邻近凹部的至少一个突起。 然后，在不暴露的情况下形成修整光致抗蚀剂以填充凹部并覆盖突起。 然后，进行修整蚀刻步骤以消除突起并且顺利地移除修整光致抗蚀剂。

    Method for forming void-free dielectric layer
    4.
    发明授权
    Method for forming void-free dielectric layer 有权
    无空隙电介质层形成方法

    公开(公告)号：US08691659B2

    公开(公告)日：2014-04-08

    申请号：US13281459

    申请日：2011-10-26

    Applicant: Ching-Pin Hsu ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Shang-Yuan Tsai ,  Li-Chiang Chen

    Inventor： Ching-Pin Hsu ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Shang-Yuan Tsai ,  Li-Chiang Chen

    IPC: H01L21/762

    CPC classification number: H01L21/76232

    Abstract: A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.

    Abstract translation: 公开了一种形成没有空隙的电介质层的方法。 首先，提供基板，包括凹部的第一应力层，设置在第一应力层上并覆盖凹部的第二应力层和嵌入凹部中的图案化光致抗蚀剂。 第二，执行第一蚀刻步骤以完全去除光致抗蚀剂，使得剩余的第二应力层形成邻近凹部的至少一个突起。 然后，在不暴露的情况下形成修整光致抗蚀剂以填充凹部并覆盖突起。 然后，进行修整蚀刻步骤以消除突起并且顺利地移除修整光致抗蚀剂。

    Method for fabricating CMOS transistor
    6.
    发明授权
    Method for fabricating CMOS transistor 有权
    制造CMOS晶体管的方法

    公开(公告)号：US08252650B1

    公开(公告)日：2012-08-28

    申请号：US13092151

    申请日：2011-04-22

    Applicant: Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

    Inventor： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

    IPC: H01L21/8234

    CPC classification number: H01L21/823807 ,  H01L21/823864

    Abstract: A method for fabricating MOS transistor includes the steps of: overlapping a second stress layer on an etching stop layer and a first stress layer at a boundary region of the substrate; forming a dielectric layer on the first stress layer and the second stress layer; performing a first etching process to partially remove the dielectric layer for exposing a portion of the second stress layer at the boundary region; performing a second etching process to partially remove the exposed portion of the second stress layer for exposing the etching stop layer; performing a third etching process to partially remove the exposed portion of the etching stop layer for exposing the first stress layer at the boundary region; and performing a fourth etching process partially remove the exposed portion of the first stress layer.

    Abstract translation: 一种用于制造MOS晶体管的方法包括以下步骤：在蚀刻停止层和基板的边界区域处的第一应力层上重叠第二应力层; 在所述第一应力层和所述第二应力层上形成介电层; 执行第一蚀刻工艺以部分去除所述电介质层以暴露所述边界区域处的所述第二应力层的一部分; 执行第二蚀刻工艺以部分地去除第二应力层的暴露部分以暴露蚀刻停止层; 执行第三蚀刻工艺以部分地去除用于在边界区域露出第一应力层的蚀刻停止层的暴露部分; 并且执行第四蚀刻工艺部分地去除第一应力层的暴露部分。

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