公开(公告)号：US20100302732A1

公开(公告)日：2010-12-02

申请号：US12851754

申请日：2010-08-06

Applicant: Chia-Hsing Chou ,  Chih-Wei Tsai ,  Chia-Hung Lu

Inventor： Chia-Hsing Chou ,  Chih-Wei Tsai ,  Chia-Hung Lu

IPC: H05K7/20

CPC classification number: H01L23/467 ,  H01L23/40 ,  H01L2023/4087 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heat-dissipating mechanism includes a first heat-dissipating device, a first positioning device, a second heat-dissipating device and a second positioning device. The first heat-dissipating device is contacted with a memory module. The first positioning device is disposed on the first heat-dissipating device and includes a protrusion. The second heat-dissipating device is connected with the first heat-dissipating device. The second positioning device has a positioning rail formed in the second heat-dissipating device and corresponding to the protrusion. The second heat-dissipating device is connected with the first heat-dissipating device when the protrusion of the first positioning device is embedded into the positioning rail second positioning device.

Abstract translation: 散热机构包括第一散热装置，第一定位装置，第二散热装置和第二定位装置。 第一散热装置与存储器模块接触。 第一定位装置设置在第一散热装置上并且包括突起。 第二散热装置与第一散热装置连接。 第二定位装置具有形成在第二散热装置中并对应于突起的定位轨道。 当第一定位装置的突起嵌入到定位轨道第二定位装置中时，第二散热装置与第一散热装置连接。

公开(公告)号：US20090106513A1

公开(公告)日：2009-04-23

申请号：US11875952

申请日：2007-10-22

Applicant: Chuang Cheng ,  Chih-Wei Tsai ,  Shih-Chieh Tai ,  Satoshi Sugawa ,  Wen-Lin Cheng

Inventor： Chuang Cheng ,  Chih-Wei Tsai ,  Shih-Chieh Tai ,  Satoshi Sugawa ,  Wen-Lin Cheng

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F11/1068 ,  G06F2212/1032

Abstract: A method for copying data in a non-volatile memory system is disclosed. The method includes calculating a number of errors of a first set of data from a source block of the non-volatile memory saved in the buffer of the controller, transmitting the first set of data saved in the buffer of the controller to a buffer of the non-volatile memory when the number of errors is lower than a threshold, and programming a destination block of the non-volatile memory with the first set of data saved in the buffer of the non-volatile memory when the number of errors is lower than the threshold.

Abstract translation: 公开了一种在非易失性存储器系统中复制数据的方法。 该方法包括从存储在控制器的缓冲器中的非易失性存储器的源块中计算第一组数据的错误数量，将保存在控制器的缓冲器中的第一组数据发送到控制器的缓冲器 当错误数量低于阈值时，非易失性存储器，并且当错误数量低于非易失性存储器的数量时，利用保存在非易失性存储器的缓冲器中的第一组数据来编程非易失性存储器的目的地块 门槛。

公开(公告)号：US20080264673A1

公开(公告)日：2008-10-30

申请号：US11790617

申请日：2007-04-26

Applicant: Cheng-Jan Chi ,  Wen-Cheng Ko ,  Sheng-Ming Chang ,  Chih-Wei Tsai

Inventor： Cheng-Jan Chi ,  Wen-Cheng Ko ,  Sheng-Ming Chang ,  Chih-Wei Tsai

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  G06F13/409 ,  H05K1/0219 ,  H05K2201/09236 ,  H05K2201/09672

Abstract: A positive differential signal trace and a negative differential signal trace are formed on different layers of a printed circuit board. A first ground trace is formed on the layer on which the positive differential signal trace is formed, and a second ground trace is formed on the layer on which the negative differential signal trace is formed. An insulation layer is positioned between the two layers and has a predetermined thickness. A differential mode impedance and a common mode impedance of differential signals are dependent on the predetermined thickness of the insulation layer, width and thickness of each differential signal trace, and a space between each differential signal trace and the corresponding ground trace formed on the same layer.

Abstract translation: 在印刷电路板的不同层上形成正差分信号迹线和负差分信号迹线。 第一接地迹线形成在其上形成正差分信号迹线的层上，并且在形成有负差分信号迹线的层上形成第二接地迹线。 绝缘层位于两层之间并具有预定的厚度。 差分信号的差模阻抗和共模阻抗取决于绝缘层的预定厚度，每个差分信号迹线的宽度和厚度，以及每个差分信号迹线与形成在同一层上的对应接地迹线之间的间隔 。

公开(公告)号：US07235989B2

公开(公告)日：2007-06-26

申请号：US11233035

申请日：2005-09-23

Applicant: Pao-Nan Li ,  Chih-Wei Tsai

Inventor： Pao-Nan Li ,  Chih-Wei Tsai

IPC: G01R31/02

CPC classification number: G01R1/06772

Abstract: An electrical test device including a substrate and a plurality of test pads. The test pads are disposed on a second surface of the substrate. Each test pad has a test hole, and first and second isolation slots. The first isolation slot is disposed on the periphery of the test hole, and defines a signal region for connecting a signal terminal of a test probe. The second isolation slot is disposed on the periphery of the first isolation slot, and a ground region is defined between the first and second isolation slots. The ground region is used for connecting a ground terminal of the test probe. The test pad can match with the test probe so that the test probe can connect to the test pad for providing signal to the test probe. The electrical test device can easily measure the real electrical characteristic of the signal from the substrate.

Abstract translation: 一种电测试装置，包括基板和多个测试垫。 测试垫设置在基板的第二表面上。 每个测试垫具有测试孔，以及第一和第二隔离槽。 第一隔离槽设置在测试孔的周边，并且限定用于连接测试探针的信号端子的信号区域。 第二隔离槽设置在第一隔离槽的周边上，并且在第一和第二隔离槽之间限定接地区域。 接地区域用于连接测试探头的接地端子。 测试垫可以与测试探针匹配，以便测试探头可以连接到测试垫，以便向测试探针提供信号。 电气测试装置可以容易地测量来自衬底的信号的实际电特性。

公开(公告)号：US20070126510A1

公开(公告)日：2007-06-07

申请号：US11488821

申请日：2006-07-19

Applicant: Chih-Wei Tsai

Inventor： Chih-Wei Tsai

IPC: H03F3/04

CPC classification number: H03F3/72 ,  H03F3/181

Abstract: This invention discloses an audio process circuit structure and process method applying to a video/audio apparatus that at least comprises an audio signal detection unit, an OR gate logic circuit unit, an AND gate logic circuit unit and an audio amplifier process unit. The audio signal detection unit also comprises a coupling capacitor, a signal amplifier circuit, a DC level shift circuit, a charge circuit and a switch circuit. This audio signal detection unit transfers different amplitude and frequency of the signal to be a high or low DC logic level signal. The high DC logic level signal is an audio signal and the low DC logic level signal is a noise. When the noise is inputted to the audio signal detection unit and a mute control signal is outputted by the audio signal detection unit to disable the audio amplifier process unit so as to prohibit the noise to output.

Abstract translation: 本发明公开了一种应用于至少包括音频信号检测单元，或门逻辑电路单元，与门逻辑电路单元和音频放大器处理单元的视频/音频设备的音频处理电路结构和处理方法。 音频信号检测单元还包括耦合电容器，信号放大器电路，直流电平移位电路，充电电路和开关电路。 该音频信号检测单元将信号的不同幅度和频率传送为高或低DC逻辑电平信号。 高DC逻辑电平信号是音频信号，低直流逻辑电平信号是噪声。 当噪声被输入到音频信号检测单元，并且由音频信号检测单元输出静音控制信号以禁用音频放大器处理单元以便禁止噪声输出。

公开(公告)号：US20060087333A1

公开(公告)日：2006-04-27

申请号：US11233035

申请日：2005-09-23

Applicant: Pao-Nan Li ,  Chih-Wei Tsai

Inventor： Pao-Nan Li ,  Chih-Wei Tsai

IPC: G01R31/02

CPC classification number: G01R1/06772

Abstract: The invention relates to an electrical test device having isolation slot. The electrical test device comprises a substrate and a plurality of test pads. The test pads are disposed on a second surface of the substrate. Each test pads has a test hole, a first isolation slot and a second isolation slot. The first isolation slot is disposed on the periphery of the test hole, and defines a signal region for connecting a signal terminal of a test probe. The second isolation slot is disposed on the periphery of the first isolation slot, and a ground region is defined between the first isolation slot and the second isolation slot. The ground region is used for connecting a ground terminal of the test probe. The test pad of the invention can match with the test probe so that the test probe can connect to the test pad for providing signal to the test probe. Therefore, the electrical test device can be utilized to easily measure the real electrical characteristic of the signal from the substrate.

Abstract translation: 本发明涉及具有隔离槽的电测试装置。 电测试装置包括基板和多个测试垫。 测试垫设置在基板的第二表面上。 每个测试垫具有测试孔，第一隔离槽和第二隔离槽。 第一隔离槽设置在测试孔的周边，并且限定用于连接测试探针的信号端子的信号区域。 第二隔离槽设置在第一隔离槽的周边上，并且在第一隔离槽和第二隔离槽之间限定接地区域。 接地区域用于连接测试探头的接地端子。 本发明的测试垫可以与测试探针相匹配，使得测试探头可以连接到测试垫，以向测试探针提供信号。 因此，电气测试装置可以用于容易地测量来自衬底的信号的实际电特性。

公开(公告)号：US20130128367A1

公开(公告)日：2013-05-23

申请号：US13492575

申请日：2012-06-08

Applicant: Chih-Wei Tsai ,  Jer-Liang Yeh

Inventor： Chih-Wei Tsai ,  Jer-Liang Yeh

IPC: G02B3/14

CPC classification number: G02B3/14

Abstract: An electrode structure, applied to a liquid lens, comprises: a first annular body; a plurality of first connecting parts, connected to the first annular body and extended radially outward from the center of the first annular body; a second annular body; and a plurality of the second connecting parts, connected the second annular body and extended radially inward into the center of the second annular body. Wherein, the first annular body and the second annular body are on the same plane, the center of the first annular body is concentric with the center of the second annular body, the first connecting parts and the second connecting parts are mutually interlaced and arranged in circular permutation.

Abstract translation: 施加到液体透镜的电极结构包括：第一环形体; 多个第一连接部分，连接到第一环形体并从第一环形体的中心径向向外延伸; 第二环形体; 以及多个所述第二连接部分，连接所述第二环形体并径向向内延伸到所述第二环形体的中心。 其中，第一环状体和第二环状体位于同一平面上，第一环状体的中心与第二环状体的中心同心，第一连接部和第二连接部相互交织并排列成 循环置换

公开(公告)号：US08332607B2

公开(公告)日：2012-12-11

申请号：US12183229

申请日：2008-07-31

Applicant: Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

Inventor： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract translation: 非易失性存储器存储设备具有非易失性存储器，例如闪存，以及耦合到非易失性存储器的控制器。 控制器包括多个控制电路和仲裁电路。 每个控制电路被配置为产生用于更新用于非易失性存储器的芯片使能（CE）信号的请求，并且仲裁电路被配置为确定何时请求被确认。 当仲裁电路已经接收到控制电路的所有请求时，仲裁电路向控制电路产生确认信号。 当请求被确认时，更新用于非易失性存储器的CE信号。

公开(公告)号：US08220144B2

公开(公告)日：2012-07-17

申请号：US12273519

申请日：2008-11-18

Applicant: Chia-Hsing Chou ,  Chih-Wei Tsai

Inventor： Chia-Hsing Chou ,  Chih-Wei Tsai

IPC: H05K3/30

CPC classification number: H05K1/0236 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/185 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/10022 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for improving EBG (electromagnetic bandgap) structures is provided. First, a multi-layer board having at least one EBG unit is provided. Then, a maximum input impedance of the EBG unit under a predetermined frequency band is measured, in which a frequency corresponding to the maximum input impedance is a resonance frequency, and a capacitance is determined based on the resonance frequency. Besides, a minimum input impedance of the EBG unit is measured, and a logarithmic value corresponding to the maximum input impedance and a logarithmic value corresponding to the minimum input impedance are obtained so as to determine a resistance. Finally, an electronic device having the capacitance and the resistance is coupled to the EBG unit in parallel.

Abstract translation: 提供了一种改善EBG（电磁带隙）结构的方法。 首先，提供具有至少一个EBG单元的多层板。 然后，测量在预定频带下的EBG单元的最大输入阻抗，其中对应于最大输入阻抗的频率是谐振频率，并且基于谐振频率确定电容。 此外，测量EBG单元的最小输入阻抗，并且获得对应于最大输入阻抗的对数值和对应于最小输入阻抗的对数值，以便确定电阻。 最后，具有电容和电阻的电子装置并联耦合到EBG单元。

公开(公告)号：US20100030933A1

公开(公告)日：2010-02-04

申请号：US12183229

申请日：2008-07-31

Applicant: Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

Inventor： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

IPC: G06F13/12 ,  G06F12/02

CPC classification number: G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract translation: 非易失性存储器存储设备具有非易失性存储器，例如闪存，以及耦合到非易失性存储器的控制器。 控制器包括多个控制电路和仲裁电路。 每个控制电路被配置为产生用于更新用于非易失性存储器的芯片使能（CE）信号的请求，并且仲裁电路被配置为确定何时请求被确认。 当仲裁电路已经接收到控制电路的所有请求时，仲裁电路向控制电路产生确认信号。 当请求被确认时，更新用于非易失性存储器的CE信号。