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    Borderless contacts in semiconductor devices
    1.
    发明授权
    Borderless contacts in semiconductor devices 有权

    公开(公告)号：US08741752B2

    公开(公告)日：2014-06-03

    申请号：US13605144

    申请日：2012-09-06

    Applicant: Su Chen Fan ,  David V. Horak ,  Sivananda K. Kanakasabapathy

    Inventor： Su Chen Fan ,  David V. Horak ,  Sivananda K. Kanakasabapathy

    IPC: H01L21/28

    CPC classification number: H01L21/28 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/78

    Abstract: A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.

    Borderless contacts in semiconductor devices
    2.
    发明授权
    Borderless contacts in semiconductor devices 有权
    半导体器件中的无边界接触

    公开(公告)号：US08637908B2

    公开(公告)日：2014-01-28

    申请号：US13188789

    申请日：2011-07-22

    Applicant: Su Chen Fan ,  David V. Horak ,  Sivananda K. Kanakasabapathy

    Inventor： Su Chen Fan ,  David V. Horak ,  Sivananda K. Kanakasabapathy

    IPC: H01L29/66 ,  H01L21/44

    CPC classification number: H01L21/28 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/78

    Abstract: A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.

    Abstract translation: 一种方法包括在衬底的暴露部分和设置在衬底上的栅极堆叠上沉积虚拟填充材料，去除虚拟填充材料的部分以暴露衬底的部分，在衬底的暴露部分上形成间隔材料层 ，虚拟填充材料和栅极堆叠，去除间隔物材料层的部分以暴露衬底和虚拟填充材料的部分，在间隔材料，衬底和栅极堆叠的暴露部分上沉积介电层 去除所述介电层的部分以暴露所述间隔物材料的部分，去除所述间隔物材料的暴露部分以暴露所述基底的部分并且限定所述电介质层中的至少一个腔，以及在所述至少一个腔中沉积导电材料 。

    Circuit Board Circuit Apparatus and Light Source Apparatus
    4.
    发明申请
    Circuit Board Circuit Apparatus and Light Source Apparatus 有权
    电路板电路设备和光源设备

    公开(公告)号：US20130120993A1

    公开(公告)日：2013-05-16

    申请号：US13600352

    申请日：2012-08-31

    Applicant: Hua-Chen Fan ,  Te-Hen Lo ,  Cheng-Wei Chang

    Inventor： Hua-Chen Fan ,  Te-Hen Lo ,  Cheng-Wei Chang

    IPC: H05K7/06 ,  F21S4/00

    CPC classification number: H05K1/0296 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09772 ,  H05K2201/10106

    Abstract: A circuit board circuit apparatus and a light source apparatus including a substrate, a circuit layer, and at least one electronic component are disclosed. The circuit layer is formed on a surface of the substrate. The circuit layer includes a first circuit and a second circuit which are coplanar-disposed. The at least one electronic component is disposed on the circuit layer and connected with the circuit layer. Each electronic component has a first contact and a second contact. At least a part of the second circuit is disposed between the at least one electronic component and the first circuit. The at least one electronic component crosses over the second circuit, so that the second circuit penetrates through the bottom of the electronic component between the first contact and the second contact.

    Abstract translation: 公开了一种电路板电路装置和包括基板，电路层和至少一个电子部件的光源装置。 电路层形成在基板的表面上。 电路层包括共面布置的第一电路和第二电路。 至少一个电子部件设置在电路层上并与电路层连接。 每个电子部件具有第一接触和第二接触。 第二电路的至少一部分设置在至少一个电子部件和第一电路之间。 所述至少一个电子部件跨越所述第二电路，使得所述第二电路在所述第一触点和所述第二触点之间穿过所述电子部件的底部。

    MULTI-GATE FIELD-EFFECT TRANSISTORS WITH VARIABLE FIN HEIGHTS
    5.
    发明申请
    MULTI-GATE FIELD-EFFECT TRANSISTORS WITH VARIABLE FIN HEIGHTS 审中-公开
    具有可变熔接高度的多栅极场效应晶体管

    公开(公告)号：US20130082329A1

    公开(公告)日：2013-04-04

    申请号：US13251815

    申请日：2011-10-03

    Applicant: Hsueh-Chung Chen ,  Su Chen Fan ,  Theodorus E. Standaert ,  Chun-Chen Yeh

    Inventor： Hsueh-Chung Chen ,  Su Chen Fan ,  Theodorus E. Standaert ,  Chun-Chen Yeh

    IPC: H01L27/088 ,  H01L21/28 ,  H01L29/78

    CPC classification number: H01L21/823431 ,  H01L27/0886

    Abstract: Multi-gate devices and methods of their fabrication are disclosed. A multi-gate device can include a gate structure and a plurality of fins. The gate structure envelops a plurality of surfaces of the fins, which are directly on a substrate that is composed of a semiconducting material. Each of the fins provides a channel between a respective source and a respective drain, is composed of the semiconducting material and is doped. A first fin of the plurality of fins has a first height that is different from a second height of a second fin of the plurality of fins such that drive currents of the first and second fins are different. Further, the first and second fins form a respective cohesive structure of the semiconducting material with the substrate. In addition, surfaces of the substrate that border the fins are disposed at a same vertical position.

    Abstract translation: 公开了多栅极器件及其制造方法。 多栅极器件可以包括栅极结构和多个鳍。 栅极结构包围鳍片的多个表面，其直接在由半导体材料构成的衬底上。 每个翅片在相应的源和相应的漏极之间提供通道，由半导体材料组成并且被掺杂。 多个翅片的第一翅片具有与多个翅片中的第二翅片的第二高度不同的第一高度，使得第一和第二翅片的驱动电流不同。 此外，第一和第二散热片形成半导体材料与衬底的相应的内聚结构。 此外，与翅片相接的基板的表面设置在相同的垂直位置。

    Direct printing lithography system and method
    7.
    发明申请
    Direct printing lithography system and method 审中-公开
    直接印刷光刻系统及方法

    公开(公告)号：US20070289467A1

    公开(公告)日：2007-12-20

    申请号：US11454577

    申请日：2006-06-16

    Applicant: Hsueh-Chung Chen ,  Ding-Chung Lu ,  Su-Chen Fan

    Inventor： Hsueh-Chung Chen ,  Ding-Chung Lu ,  Su-Chen Fan

    IPC: B41F1/18

    CPC classification number: B41F1/18

    Abstract: A direct printing lithography system for jet-printing a photoresist on a layer in the form of a desired circuit pattern is disclosed. The system includes a computer system for containing a programmed circuit pattern and generating printing signals and a jet printing head for receiving the printing signals from the computer system and printing the photoresist on the layer in the form of the programmed circuit pattern. A direct printing lithography method is also disclosed.

    Abstract translation: 公开了一种用于以期望的电路图案形式在层上喷射印刷光致抗蚀剂的直接印刷光刻系统。 该系统包括用于容纳编程的电路图案和产生打印信号的计算机系统，以及用于从计算机系统接收打印信号并以编程的电路图案的形式在该层上打印光致抗蚀剂的喷墨打印头。 还公开了一种直接印刷光刻方法。

    Interconnect structure and method of fabricating same
    8.
    发明申请
    Interconnect structure and method of fabricating same 有权
    互连结构及其制造方法

    公开(公告)号：US20070145596A1

    公开(公告)日：2007-06-28

    申请号：US11317652

    申请日：2005-12-22

    Applicant: Hsueh-Chung Chen ,  Chine-Gie Lou ,  Ping-Liang Liu ,  Su-Chen Fan

    Inventor： Hsueh-Chung Chen ,  Chine-Gie Lou ,  Ping-Liang Liu ,  Su-Chen Fan

    IPC: H01L23/48

    CPC classification number: H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An improved interconnect structure and method of making such a device The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.

    Abstract translation: 改进的互连结构和制造这种器件的方法改进的互连电路连接半导体晶片上的另外两个分开的区域。 互连优选地使用布置在沟槽内的铜导体和使用双镶嵌工艺在低k混合电介质层中形成的通孔结构。 每个接触区域由多个通孔提供，每个通孔与沟槽导体部分连通。 从沟槽到通孔的入口对于至少一个并且优选地所有通孔结构是圆形的。

    Three dimensional IC device and alignment methods of IC device substrates
    9.
    发明申请
    Three dimensional IC device and alignment methods of IC device substrates 有权
    IC器件基板的三维IC器件和对准方法

    公开(公告)号：US20070020871A1

    公开(公告)日：2007-01-25

    申请号：US11174511

    申请日：2005-07-06

    Applicant: Hsueh-Chung Chen ,  Chine-Gie Lou ,  Su-Chen Fan

    Inventor： Hsueh-Chung Chen ,  Chine-Gie Lou ,  Su-Chen Fan

    IPC: H01L21/76

    CPC classification number: H01L21/681

    Abstract: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.

    Abstract translation: IC器件基板的对准方法。 第一IC器件衬底具有用于限定多个第一IC特征的第一前侧，与第一前侧相对的第一背面，以及形成在第一前侧或第一背面上的第一对准图案。 第二IC器件衬底具有用于限定多个第二IC特征的第二前侧，与第二前侧相对的第二后侧和形成在第二前侧或第二后侧上的第二对准图案。 应用第一光学检测器和第二光学检测器来检测第一和第二对准图案，以对准第一和第二IC器件基板。 具体地，第一和第二对准图案朝向相反方向的第一和第二光学检测器。

    System for driving plural lamps
    10.
    发明申请
    System for driving plural lamps 失效
    用于驱动多个灯的系统

    公开(公告)号：US20060145637A1

    公开(公告)日：2006-07-06

    申请号：US11314050

    申请日：2005-12-20

    Applicant: Chi-Hsiung Lee ,  Yu-Hsiao Chao ,  Che-Chen Fan Chiang ,  Cheng-Chueh Tsai ,  Shian-Nan Lin

    Inventor： Chi-Hsiung Lee ,  Yu-Hsiao Chao ,  Che-Chen Fan Chiang ,  Cheng-Chueh Tsai ,  Shian-Nan Lin

    IPC: H05B39/00

    CPC classification number: H05B41/282 ,  Y02B20/183 ,  Y10S315/05

    Abstract: A system for driving a lamp module (13) includes a converter (11), a driving circuit (12), and a pulse width modulation (PWM) controller (14). The lamp module includes a plurality of lamps. The converter converts a received voltage to a direct current (DC) voltage. The driving circuit converts the DC voltage to an alternating current (AC) voltage. The PWM controller is connected between the converter and the lamp module, for regulating the DC voltages outputted from the converter according to current flowing through the lamps of the lamp module. In one embodiment, the system includes a bus inverter controller. The bus inverter controller is connected between the driving circuit and the lamp module, for regulating a working frequency thereof and controlling the AC voltage outputted from the driving circuit when the lamps are turned on. The system has a reduced number of PWM controllers and a relatively low cost.

    Abstract translation: 用于驱动灯模块（13）的系统包括转换器（11），驱动电路（12）和脉宽调制（PWM）控制器（14）。 灯模块包括多个灯。 转换器将接收的电压转换为直流（DC）电压。 驱动电路将DC电压转换成交流（AC）电压。 PWM控制器连接在转换器和灯模块之间，用于根据流经灯模块灯的电流来调节转换器输出的直流电压。 在一个实施例中，该系统包括总线逆变器控制器。 总线逆变器控制器连接在驱动电路和灯模块之间，用于调节其工作频率并控制当灯打开时从驱动电路输出的AC电压。 该系统的PWM控制器数量减少，成本相对较低。

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