公开(公告)号：US06642112B1

公开(公告)日：2003-11-04

申请号：US09918364

申请日：2001-07-30

Applicant: Brett D. Lowe ,  John A. Smythe ,  Timothy K. Carns

Inventor： Brett D. Lowe ,  John A. Smythe ,  Timothy K. Carns

IPC: H01L218234

CPC classification number: H01L21/823842 ,  H01L21/823864 ,  H01L21/823878

Abstract: Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.

Abstract translation: 用于制造半导体器件（例如MOSFET器件）的非氧化间隔物致密化方法，并且可以在半导体制造期间实施，在间隔物致密化期间几乎没有或基本上没有聚硅氧烷粘附损失。 该方法可以实现以通过消除对附加工艺步骤（例如金属硅化物封装或多晶硅表面处理）的需要来提供优于常规方法的降低的工艺复杂性的良好的多晶硅化合物附着特性。

公开(公告)号：US07807528B1

公开(公告)日：2010-10-05

申请号：US12383534

申请日：2009-03-24

Applicant: John A. Ransom ,  Brett D. Lowe ,  Michael J. Westphal

Inventor： John A. Ransom ,  Brett D. Lowe ,  Michael J. Westphal

IPC: H01L21/8234

CPC classification number: H01L29/0847 ,  H01L23/60 ,  H01L27/0266 ,  H01L29/1087 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.

Abstract translation: 静电放电（ESD）晶体管结构包括从50微米宽的栅电极小于0.4微米的自对准外伸支架。 外部支架在集成电路的普通逻辑晶体管上制造，而不会严重影响晶体管的性能。 外伸支架用作植入物阻挡结构，以在悬臂附近的轻掺杂区域的两侧形成第一和第二漏区。 自对准外伸支架及其下方的轻掺杂区域用于将ESD事件的远离通道区域的雪崩击穿位置移动。 当较少的“热载体”电子在栅极氧化物中积聚时，耐久性得到延长。 至少100毫安的电流可以流入漏极，然后通过ESD晶体管结构超过30秒的时间，而不会导致ESD晶体管结构的灾难性故障。

公开(公告)号：US20130087883A1

公开(公告)日：2013-04-11

申请号：US13268066

申请日：2011-10-07

Applicant: James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

Inventor： James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

IPC: H01L29/06 ,  H01L21/31

CPC classification number: H01L29/0649 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11573

Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.

Abstract translation: 形成存储器阵列和外围电路隔离的方法包括在存储器阵列电路隔离沟槽的侧壁和在半导体材料中形成的外围电路隔离沟槽的化学气相沉积包含二氧化硅的衬垫。 电介质材料流过含二氧化硅的衬垫以填充阵列隔离沟槽的剩余体积，并在至少一些外围隔离沟槽中的含二氧化硅的衬垫上形成电介质衬垫。 电介质材料在不大于约500℃的温度下进行炉退火。退火的电介质材料被快速热处理至不低于约800℃的温度。含二氧化硅的材料经快速热化学气相沉积 处理的介电材料以填充所述至少一些外围隔离沟槽的剩余体积。 公开了其它方面，包括由公开的方法产生的集成电路和独立于制造方法的集成电路。

公开(公告)号：US08062941B1

公开(公告)日：2011-11-22

申请号：US13065940

申请日：2011-04-02

Applicant: John A. Ransom ,  Brett D. Lowe ,  Michael J. Westphal

Inventor： John A. Ransom ,  Brett D. Lowe ,  Michael J. Westphal

IPC: H01L21/8238

CPC classification number: H01L29/0847 ,  H01L23/60 ,  H01L27/0266 ,  H01L29/1087 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.

Abstract translation: 静电放电（ESD）晶体管结构包括从50微米宽的栅电极小于0.4微米的自对准外伸支架。 外部支架在集成电路的普通逻辑晶体管上制造，而不会严重影响晶体管的性能。 外伸支架用作植入物阻挡结构，以在悬臂附近的轻掺杂区域的两侧形成第一和第二漏区。 自对准外伸支架及其下方的轻掺杂区域用于将ESD事件的远离通道区域的雪崩击穿位置移动。 当较少的“热载体”电子在栅极氧化物中积聚时，耐久性得到延长。 至少100毫安的电流可以流入漏极，然后通过ESD晶体管结构超过30秒的时间，而不会导致ESD晶体管结构的灾难性故障。

公开(公告)号：US07508038B1

公开(公告)日：2009-03-24

申请号：US11118680

申请日：2005-04-29

Applicant: John A. Ransom ,  Brett D. Lowe ,  Michael J. Westphal

Inventor： John A. Ransom ,  Brett D. Lowe ,  Michael J. Westphal

IPC: H01L23/62

CPC classification number: H01L29/0847 ,  H01L23/60 ,  H01L27/0266 ,  H01L29/1087 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.

Abstract translation: 静电放电（ESD）晶体管结构包括从50微米宽的栅电极小于0.4微米的自对准外伸支架。 外部支架在集成电路的普通逻辑晶体管上制造，而不会严重影响晶体管的性能。 外伸支架用作植入物阻挡结构，以在悬臂附近的轻掺杂区域的两侧形成第一和第二漏区。 自对准外伸支架及其下方的轻掺杂区域用于将ESD事件的远离通道区域的雪崩击穿位置移动。 当较少的“热载体”电子在栅极氧化物中积聚时，耐久性得到延长。 至少100毫安的电流可以流入漏极，然后通过ESD晶体管结构超过30秒的时间，而不会导致ESD晶体管结构的灾难性故障。

公开(公告)号：US06849510B2

公开(公告)日：2005-02-01

申请号：US10667919

申请日：2003-09-22

Applicant: Brett D. Lowe ,  John A. Smythe ,  Timothy K. Carns

Inventor： Brett D. Lowe ,  John A. Smythe ,  Timothy K. Carns

IPC: H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/823864 ,  H01L21/823878

Abstract: Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.

Abstract translation: 用于制造半导体器件（例如MOSFET器件）的非氧化间隔物致密化方法，并且可以在半导体制造期间实施，在间隔物致密化期间几乎没有或基本上没有聚硅氧烷粘附损失。 该方法可以实现以通过消除对附加工艺步骤（例如金属硅化物封装或多晶硅表面处理）的需要来提供优于常规方法的降低的工艺复杂性的良好的多晶硅化合物附着特性。

公开(公告)号：US08461016B2

公开(公告)日：2013-06-11

申请号：US13268066

申请日：2011-10-07

Applicant: James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

Inventor： James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

IPC: H01L21/76

CPC classification number: H01L29/0649 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11573

Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.

Abstract translation: 形成存储器阵列和外围电路隔离的方法包括在存储器阵列电路隔离沟槽的侧壁和在半导体材料中形成的外围电路隔离沟槽的化学气相沉积包含二氧化硅的衬垫。 电介质材料流过含二氧化硅的衬垫以填充阵列隔离沟槽的剩余体积，并在至少一些外围隔离沟槽中的含二氧化硅的衬垫上形成电介质衬垫。 电介质材料在不大于约500℃的温度下进行炉退火。退火的电介质材料被快速热处理至不低于约800℃的温度。含二氧化硅的材料经快速热化学气相沉积 处理的介电材料以填充所述至少一些外围隔离沟槽的剩余体积。 公开了其它方面，包括由公开的方法产生的集成电路和独立于制造方法的集成电路。

公开(公告)号：US08093121B1

公开(公告)日：2012-01-10

申请号：US13248520

申请日：2011-09-29

Applicant: John A. Ransom ,  Brett D. Lowe ,  Michael J. Westphal

Inventor： John A. Ransom ,  Brett D. Lowe ,  Michael J. Westphal

IPC: H01L21/8238

CPC classification number: H01L29/0847 ,  H01L23/60 ,  H01L27/0266 ,  H01L29/1087 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.

Abstract translation: 静电放电（ESD）晶体管结构包括从50微米宽的栅电极小于0.4微米的自对准外伸支架。 外部支架在集成电路的普通逻辑晶体管上制造，而不会严重影响晶体管的性能。 外伸支架用作植入物阻挡结构，以在悬臂附近的轻掺杂区域的两侧形成第一和第二漏区。 自对准外伸支架及其下方的轻掺杂区域用于将ESD事件的远离通道区域的雪崩击穿位置移动。 当较少的“热载体”电子在栅极氧化物中积聚时，耐久性得到延长。 至少100毫安的电流可以流入漏极，然后通过ESD晶体管结构超过30秒的时间，而不会导致ESD晶体管结构的灾难性故障。

公开(公告)号：US07927944B1

公开(公告)日：2011-04-19

申请号：US12807669

申请日：2010-09-10

Applicant: John A. Ransom ,  Brett D. Lowe ,  Michael J. Westphal

Inventor： John A. Ransom ,  Brett D. Lowe ,  Michael J. Westphal

IPC: H01L21/8234

CPC classification number: H01L29/0847 ,  H01L23/60 ,  H01L27/0266 ,  H01L29/1087 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.