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    Variable breakdown transient voltage suppressor
    2.
    发明授权
    Variable breakdown transient voltage suppressor 有权
    可变击穿瞬态电压抑制器

    公开(公告)号：US08730629B2

    公开(公告)日：2014-05-20

    申请号：US13334598

    申请日：2011-12-22

    申请人： Avinash Srikrishnan Kashyap ,  Stanislav Ivanovich Soloviev

    发明人： Avinash Srikrishnan Kashyap ,  Stanislav Ivanovich Soloviev

    IPC分类号： H02H3/22

    CPC分类号： H01L29/36 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/861 ,  H01L29/8618

    摘要： A semiconductor die includes a substrate comprising a first layer of a first wide band gap semiconductor material having a first conductivity, a second layer of a second wide band gap semiconductor material having a second conductivity different from the first conductivity, in electrical contact with the first layer, a third layer of a third wide band gap semiconductor material having a third conductivity different from the first conductivity and second conductivity, in electrical contact with the second layer, a fourth layer of a fourth wide band gap semiconductor material having the second conductivity, in electrical contact with the third layer, and a fifth layer of a fifth wide band gap semiconductor material having the first conductivity and in electrical contact with the fourth layer, wherein the first layer, the second layer, the third layer, the fourth layer, and the fifth layer are sequentially arranged to form a structure.

    摘要翻译： 半导体管芯包括：衬底，其包括具有第一导电性的第一宽带隙半导体材料的第一层，具有与第一导电性不同的第二导电性的第二宽带隙半导体材料的第二层与第一导电 具有与第一导电性和第二导电性不同的第三导电性的与第二层电接触的第三宽带隙半导体材料的第三层，具有第二导电性的第四宽带隙半导体材料的第四层， 与第三层电接触，以及具有第一导电性并与第四层电接触的第五宽带隙半导体材料的第五层，其中第一层，第二层，第三层，第四层， 并且顺序地布置第五层以形成结构。

    VARIABLE BREAKDOWN TRANSIENT VOLTAGE SUPPRESSOR
    4.
    发明申请
    VARIABLE BREAKDOWN TRANSIENT VOLTAGE SUPPRESSOR 有权
    可变断开瞬态电压抑制器

    公开(公告)号：US20130163139A1

    公开(公告)日：2013-06-27

    申请号：US13334598

    申请日：2011-12-22

    申请人： Avinash Srikrishnan Kashyap ,  Stanislav Ivanovich Soloviev

    发明人： Avinash Srikrishnan Kashyap ,  Stanislav Ivanovich Soloviev

    IPC分类号： H02H3/22 ,  H01L29/20 ,  H01L21/66 ,  H01L29/16

    CPC分类号： H01L29/36 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/861 ,  H01L29/8618

    摘要： A semiconductor die includes a substrate comprising a first layer of a first wide band gap semiconductor material having a first conductivity, a second layer of a second wide band gap semiconductor material having a second conductivity different from the first conductivity, in electrical contact with the first layer, a third layer of a third wide band gap semiconductor material having a third conductivity different from the first conductivity and second conductivity, in electrical contact with the second layer, a fourth layer of a fourth wide band gap semiconductor material having the second conductivity, in electrical contact with the third layer, and a fifth layer of a fifth wide band gap semiconductor material having the first conductivity and in electrical contact with the fourth layer, wherein the first layer, the second layer, the third layer, the fourth layer, and the fifth layer are sequentially arranged to form a structure.

    摘要翻译： 半导体管芯包括：衬底，其包括具有第一导电性的第一宽带隙半导体材料的第一层，具有与第一导电性不同的第二导电性的第二宽带隙半导体材料的第二层与第一导电 具有与第一导电性和第二导电性不同的第三导电性的与第二层电接触的第三宽带隙半导体材料的第三层，具有第二导电性的第四宽带隙半导体材料的第四层， 与第三层电接触，以及具有第一导电性并与第四层电接触的第五宽带隙半导体材料的第五层，其中第一层，第二层，第三层，第四层， 并且顺序地布置第五层以形成结构。

    System for transient voltage suppressors
    8.
    发明授权
    System for transient voltage suppressors 有权
    瞬态电压抑制器系统

    公开(公告)号：US08530902B2

    公开(公告)日：2013-09-10

    申请号：US13281638

    申请日：2011-10-26

    申请人： Avinash Srikrishnan Kashyap ,  David Mulford Shaddock ,  Emad Andarawis Andarawis ,  Peter Micah Sandvik ,  Stephen Daley Arthur ,  Vinayak Tilak

    发明人： Avinash Srikrishnan Kashyap ,  David Mulford Shaddock ,  Emad Andarawis Andarawis ,  Peter Micah Sandvik ,  Stephen Daley Arthur ,  Vinayak Tilak

    IPC分类号： H01L29/15

    CPC分类号： H01L21/56 ,  H01L23/3185 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/861 ,  H01L29/8618 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.

    摘要翻译： 提供了形成碳化硅瞬态电压抑制器（TVS）组件的方法和用于瞬态电压抑制器（TVS）组件的系统。 TVS组件包括台面结构中的半导体管芯，其包括具有第一极性的导电率的第一宽带隙半导体的第一层，具有第二极导电率的第一或第二宽带隙半导体的第二层 极性与第一层电接触，其中第二极性不同于第一极性。 TVS组件还包括具有与第二层电接触的第一极性的导电性的第一，第二或第三宽带隙半导体的第三层。 相对于具有第一极性的导电性的层，具有第二极性的导电性的层被轻掺杂。