公开(公告)号：US07065140B1

公开(公告)日：2006-06-20

申请号：US09414307

申请日：1999-10-06

申请人： David W. Ritter ,  Ara Bicakci

发明人： David W. Ritter ,  Ara Bicakci

IPC分类号： H04B1/66

CPC分类号： H04N7/181

摘要： A method and apparatus for receiving video signals from a plurality of video cameras, such as in a video surveillance system. The video cameras are each coupled to provide a video signal to a respective input of a multiplexer. The multiplexer routes a selected one of the video signals to a video decoder. The video decoder receives the selected video signal and is conditioned according to the video signal. This includes synchronizing the video decoder to a frequency and phase of the video signal, controlling a gain level for the video signal and adjusting a dc clamping level for dc restoration of the video signal. Parameters representative of each of these quantities are stored in association with the identity of the corresponding video camera. The video decoder also places each video signal into a format suitable for storage in a storage device and for display by a display device. As the multiplexer is utilized to cycle through the cameras according to a sequence, the parameters for each camera are retrieved and utilized to initialize the video decoder for decoding the video signal received from the corresponding camera. As a result, the amount of time required to condition the video decoder according to the video signal received from each camera is significantly reduced. Accordingly, the present invention allows a surveillance system to cycle through a plurality of cameras in less time than prior systems having a single decoder, but without higher costs associated with prior systems which employ multiple video decoders.

摘要翻译： 一种用于从诸如在视频监控系统中的多个摄像机接收视频信号的方法和装置。 摄像机各自被耦合以向多路复用器的相应输入端提供视频信号。 复用器将选定的一个视频信号路由到视频解码器。 视频解码器接收所选择的视频信号，并根据视频信号进行调节。 这包括将视频解码器与视频信号的频率和相位同步，控制视频信号的增益电平并调整直流钳位电平以直接恢复视频信号。 代表这些数量中的每一个的参数与相应的摄像机的身份相关联地存储。 视频解码器还将每个视频信号放置成适合于存储在存储设备中并由显示设备显示的格式。 由于多路复用器被用于根据序列循环摄像机，因此检索并利用每个摄像机的参数来初始化视频解码器，以对从相应摄像机接收的视频信号进行解码。 结果，根据从每个摄像机接收的视频信号来调节视频解码器所需的时间量显着减少。 因此，本发明允许监视系统在比具有单个解码器的现有系统更少的时间内循环多个摄像机，但是与使用多个视频解码器的现有系统相关联的成本较高。

公开(公告)号：US06870928B1

公开(公告)日：2005-03-22

申请号：US09866525

申请日：2001-05-25

申请人： Cormac S. Conroy ,  Samuel W. Sheng ,  Ara Bicakci ,  John DeCelles ,  Sang-Soo Lee

发明人： Cormac S. Conroy ,  Samuel W. Sheng ,  Ara Bicakci ,  John DeCelles ,  Sang-Soo Lee

IPC分类号： H04L25/02 ,  H04L27/00 ,  H04M1/738 ,  H04M11/06 ,  H04M1/00

CPC分类号： H04L27/0002 ,  H04L25/0266 ,  H04M1/738 ,  H04M11/062

摘要： A line interface couples signals between a data transceiver and a transmission line having a load impedance Z. The line interface includes a transformer, a driver circuit for supplying a transmit signal from the data transceiver to the transformer, and a receiver circuit for receiving a receive signal from the transformer. The transformer includes a first port coupled to the transmission line, a second port coupled to the driver circuit, a third port coupled to the receiver circuit, a first winding part having a turns ratio of 1: n, where n>1, for coupling the transmit signal from the second port to the first port, and a second winding part having a turns ratio of 1: m, where m

摘要翻译： 线路接口在数据收发器和具有负载阻抗Z的传输线之间耦合信号。线路接口包括变压器，用于从数据收发器向变压器提供发送信号的驱动器电路，以及用于接收接收器的接收器电路 来自变压器的信号。 变压器包括耦合到传输线的第一端口，耦合到驱动器电路的第二端口，耦合到接收器电路的第三端口，具有匝数比为1：n的第一绕组部件，其中n> 1，用于耦合 从第二端口到第一端口的发送信号和匝数比为1：m的第二绕组部分，其中m

公开(公告)号：US06724219B1

公开(公告)日：2004-04-20

申请号：US09882499

申请日：2001-06-15

申请人： Chun-Sup Kim ,  Ara Bicakci ,  Cormac S. Conroy ,  Sang-Soo Lee

发明人： Chun-Sup Kim ,  Ara Bicakci ,  Cormac S. Conroy ,  Sang-Soo Lee

IPC分类号： H04B303

CPC分类号： H04L25/0278 ,  H04L1/0001 ,  H04L25/028

摘要： A line driver for coupling a data transceiver to a transmission line having a load impedance via a transformer with a turns ratio of 1:n includes an input port for receiving an input signal voltage from the data transceiver, an output port for supplying an output signal voltage to the transformer, and an amplifier circuit for amplifying the input signal voltage. The amplifier circuit includes a first output stage, a second output stage coupled to the output port, an output resistor coupled to the first output stage, a feedback path from the first output stage to an input of the amplifier circuit, and a line matching network coupled between the first output stage and the second output stage, for compensating variations in the load impedance, so that a synthesized output impedance of the line driver substantially matches an actual load impedance Z of the transmission line.

摘要翻译： 用于将数据收发器耦合到具有匝数比为1：n的变压器的具有负载阻抗的传输线的线路驱动器包括用于从数据收发器接收输入信号电压的输入端口，用于提供输出信号的输出端口 变压器的电压和用于放大输入信号电压的放大器电路。 放大器电路包括第一输出级，耦合到输出端的第二输出级，耦合到第一输出级的输出电阻，从第一输出级到放大器电路的输入的反馈路径，以及线匹配网络 耦合在第一输出级和第二输出级之间，用于补偿负载阻抗的变化，使得线路驱动器的合成输出阻抗基本上与传输线的实际负载阻抗Z匹配。

公开(公告)号：US20110090824A1

公开(公告)日：2011-04-21

申请号：US12603448

申请日：2009-10-21

申请人： Arezou Khatibi ,  Ara Bicakci ,  Rainer Gaethke

发明人： Arezou Khatibi ,  Ara Bicakci ,  Rainer Gaethke

IPC分类号： H04B1/44 ,  H03K5/00

CPC分类号： H03H11/1213

摘要： Techniques for low-pass filtering with high quality factor (Q). In an exemplary embodiment, an input current is coupled to the drain of a first transistor. The drain and the gate of the first transistor are coupled together by a resistor R1, and the drain is coupled to a reference voltage by a first capacitor C1. The gate is coupled to a reference voltage by a second capacitor C2. The gate is further coupled to the gate of a second transistor, and an output current is coupled to the drain of the second transistor. In another exemplary embodiment, further passive elements may be coupled to generate an odd-order low-pass transfer characteristic. Multiple filters may be cascaded in series to synthesize a filter having arbitrary order.

摘要翻译： 具有高品质因数（Q）的低通滤波技术。 在示例性实施例中，输入电流耦合到第一晶体管的漏极。 第一晶体管的漏极和栅极由电阻器R1耦合在一起，漏极通过第一电容器C1耦合到参考电压。 栅极通过第二电容器C2耦合到参考电压。 栅极还耦合到第二晶体管的栅极，并且输出电流耦合到第二晶体管的漏极。 在另一示例性实施例中，可以连接另外的无源元件以产生奇数低通传输特性。 多个滤波器可以串联级联以合成具有任意顺序的滤波器。

公开(公告)号：US20080246515A1

公开(公告)日：2008-10-09

申请号：US11696477

申请日：2007-04-04

申请人： Gurjinder Singh ,  Ara Bicakci

发明人： Gurjinder Singh ,  Ara Bicakci

IPC分类号： H03K5/00

CPC分类号： G01R31/31917 ,  G01R31/3191

摘要： An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circuit configured to generate the reference signal in response to a first control signal. The plurality of elements may each be configured to generate an intermediate test signal. One of the intermediate test signals may be presented as the test signal by activating one of the test elements, in response to a second control signal. The logic circuit may be configured to generate (i) the first control signal and (ii) the second control signal, each in response to the difference signal.

摘要翻译： 一种包括比较器电路，参考电路，多个元件和逻辑电路的装置。 比较器电路可以被配置为响应于（i）参考信号和（ii）测试信号而产生差分信号。 参考电路被配置为响应于第一控制信号而产生参考信号。 多个元件可以各自被配置为产生中间测试信号。 响应于第二控制信号，可以通过激活测试元件之一来呈现中间测试信号之一作为测试信号。 逻辑电路可以被配置为响应于差异信号而产生（i）第一控制信号和（ii）第二控制信号。

公开(公告)号：US07397295B2

公开(公告)日：2008-07-08

申请号：US11345929

申请日：2006-02-02

申请人： Ara Bicakci

发明人： Ara Bicakci

IPC分类号： H03L5/00

CPC分类号： H04N5/18 ,  H03F1/14 ,  H03F3/45475 ,  H03F2200/453 ,  H03F2203/45552

摘要： An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a video input signal having a voltage. The second circuit may have a finite input resistance configured to generate a current in response to presenting the voltage across the finite input resistance. The third circuit may be configured to cancel the current by (i) generating the current in response to presenting the voltage across a replica resistor having a resistance similar to the finite input resistance and (ii) passing the current away from the apparatus.

摘要翻译： 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以被配置为产生具有电压的视频输入信号。 第二电路可以具有有限的输入电阻，其被配置为响应于跨越有限输入电阻呈现电压而产生电流。 第三电路可以被配置为通过（i）响应于呈现具有类似于有限输入电阻的电阻的复制电阻器的电压而产生电流，并且（ii）使电流远离设备。

公开(公告)号：US06897798B1

公开(公告)日：2005-05-24

申请号：US10765387

申请日：2004-01-26

申请人： Ara Bicakci ,  Gurjinder Singh

发明人： Ara Bicakci ,  Gurjinder Singh

IPC分类号： H03M1/06 ,  H03M1/74 ,  H03M1/66

CPC分类号： H03M1/0678 ,  H03M1/74

摘要： A method and apparatus control switching noise in a digital-to-analog interface in a mixed-signal circuit. The digital-to-analog interface includes a first plurality (K) of switching elements and a second plurality (M) of dummy switching elements, the second plurality (M) being smaller than the first plurality (K). The switching noise control includes (a) receiving a digital data signal, (b) determining a number (N) of the switching elements to be switched for the digital data signal, and (c) switching the second plurality (M) less the number (N) of the dummy switching elements simultaneously with switching the number (N) of the switching elements.

摘要翻译： 一种方法和装置控制混合信号电路中的数模转换接口中的开关噪声。 数模转换接口包括开关元件的第一多个（K）和第二多个（M）的虚拟开关元件，第二多个（M）小于第一多个（K）。 开关噪声控制包括：（a）接收数字数据信号，（b）确定数字数据信号要切换的开关元件的数量（N），以及（c）将第二多个（M） （N）个开关元件的数量（N）同时进行。

公开(公告)号：US20100305899A1

公开(公告)日：2010-12-02

申请号：US12475262

申请日：2009-05-29

申请人： Joseph Czompo ,  Ara Bicakci

发明人： Joseph Czompo ,  Ara Bicakci

IPC分类号： G06F15/00

CPC分类号： G01C21/16 ,  G01C25/005

摘要： The subject matter disclosed herein relates to a system and method for receiving a plurality of signals generated by a plurality of sensors adapted to detect physical movement of a mobile device with respect to a plurality of coordinate axes. A time at which at least one of the received signals is digitized is delayed to provide an output of digitized versions of the received plurality of signals synchronized with respect to a common point in time.

摘要翻译： 本文公开的主题涉及一种用于接收由适合于检测移动设备相对于多个坐标轴的物理移动的多个传感器产生的多个信号的系统和方法。 将接收到的信号中的至少一个数字化的时间延迟，以提供相对于公共时间点同步的接收到的多个信号的数字化版本的输出。

公开(公告)号：US20070176645A1

公开(公告)日：2007-08-02

申请号：US11345929

申请日：2006-02-02

申请人： Ara Bicakci

发明人： Ara Bicakci

IPC分类号： G01R19/00

CPC分类号： H04N5/18 ,  H03F1/14 ,  H03F3/45475 ,  H03F2200/453 ,  H03F2203/45552

摘要： An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a video input signal having a voltage. The second circuit may have a finite input resistance configured to generate a current in response to presenting the voltage across the finite input resistance. The third circuit may be configured to cancel the current by (i) generating the current in response to presenting the voltage across a replica resistor having a resistance similar to the finite input resistance and (ii) passing the current away from the apparatus.

摘要翻译： 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以被配置为产生具有电压的视频输入信号。 第二电路可以具有被配置为响应于在有限输入电阻上呈现电压而产生电流的有限输入电阻。 第三电路可以被配置为通过（i）响应于呈现具有类似于有限输入电阻的电阻的复制电阻器的电压而产生电流，并且（ii）使电流远离设备。

公开(公告)号：US06967609B1

公开(公告)日：2005-11-22

申请号：US10987240

申请日：2004-11-12

申请人： Ara Bicakci ,  Gurjinder Singh

发明人： Ara Bicakci ,  Gurjinder Singh

IPC分类号： H03K17/041 ,  H03K17/16 ,  H03M1/06 ,  H03M1/66 ,  H03M1/74

CPC分类号： H03K17/04106 ,  H03K17/165 ,  H03M1/0604 ,  H03M1/0682 ,  H03M1/745 ,  H03M1/747

摘要： A circuit dynamically biases switching elements in a current-steering digital-to-analog converter (DAC), The DAC includes, in each cell, a current source coupled to a current node, a first switching element coupled between the current node and a first DAC output node, and a second switching element coupled between the current node and a second DAC output node. The circuit includes first and second inputs coupled to the first and second DAC output nodes, respectively, first and second outputs coupled to the first and second switching elements, respectively, and a third output coupled to the first and second switching elements. The first and second outputs provide a first ON bias voltage and a second ON bias voltage to control the first and second switching elements, respectively, such that a voltage at the current node is maintained at a predetermined voltage. The third output provides a common OFF bias voltage.

摘要翻译： 电路动态地偏置电流转向数模转换器（DAC）中的开关元件，DAC在每个单元中包括耦合到当前节点的电流源，耦合在当前节点和第一 DAC输出节点和耦合在当前节点和第二DAC输出节点之间的第二开关元件。 电路包括分别耦合到第一和第二DAC输出节点的第一和第二输入，分别耦合到第一和第二开关元件的第一和第二输出以及耦合到第一和第二开关元件的第三输出。 第一和第二输出提供第一ON偏置电压和第二ON偏置电压以分别控制第一和第二开关元件，使得当前节点处的电压保持在预定电压。 第三个输出提供一个公共的偏置偏置电压。