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公开(公告)号：US20110210877A1
公开(公告)日：2011-09-01
申请号：US12715102
申请日：2010-03-01
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , H03M1/164
摘要： Calibration methods and structures are provided for pipelined analog-to-digital converter systems. They are arranged to process samples of the digital codes with an algorithm that is preferably configured to repeatedly update an estimate of the transfer function with the difference between one of the input signals and the analog equivalent of the corresponding digital code. The calibration methods and structures are further configured to calibrate the transfer function of the converter stage wherein the samples are selected in accordance with various steps. These steps can include the step of injecting dither signals into a flash portion and an MDAC portion of the converter stage to thereby maintain dynamic range. They can also include the step of limiting the samples to those processed through a selected subrange of the subranges. They can further include the step of limiting the samples to those in which the absolute value of the input signals is less that 0.25 of the selected subrange and the absolute value of the dither signals is less that 0.25 of the selected subrange. If the selected subrange is not a central subrange, the steps can further include the step of shifting the samples by a distance between the selected subrange and the central subrange.
摘要翻译： 为流水线模数转换器系统提供校准方法和结构。 它们被布置成用算法处理数字代码的样本，该算法优选地被配置为用输入信号中的一个和对应的数字代码的模拟等效物之间的差重复更新传递函数的估计。 校准方法和结构还被配置为校准转换器级的传递函数，其中根据各种步骤选择样本。 这些步骤可以包括将抖动信号注入转换器级的闪存部分和MDAC部分，从而保持动态范围的步骤。 它们还可以包括将样品限制在通过所选子范围的子范围进行处理的样品的步骤。 它们还可以包括将样本限制为其中输入信号的绝对值小于所选子范围的0.25并且抖动信号的绝对值小于所选子范围的0.25的步骤。 如果选择的子范围不是中央子范围，则步骤还可以包括将样本移位所选子范围和中心子范围之间的距离的步骤。
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公开(公告)号：US20100301930A1
公开(公告)日：2010-12-02
申请号：US12471688
申请日：2009-05-26
IPC分类号： H03H11/24
CPC分类号： H03K17/161 , H03H19/004
摘要： A system and method are provided to reduce the influence of parasitic capacitance at the drain and source of MOS transistors of a sampling circuit. In one embodiment, the bulk is left floating during a first phase and refreshed during a second phase. During the first phase, the effective parasitic contribution of the drain or source of a MOS transistor is lower due to the series combination of Cj and Cw capacitances. In another embodiment, a large resistance provides a path from a reference voltage to the bulk of a MOS transistor, thereby resulting in an effective parasitic capacitance of the series combination of Cj and Cw. Advantageously, the parasitic capacitance is reduced as well as its non-linear effect, the operating speed is improved, as well as the signal distortion and noise.
摘要翻译： 提供了一种系统和方法，以减少采样电路的MOS晶体管的漏极和源极上的寄生电容的影响。 在一个实施例中，体积在第一阶段期间保持浮动并在第二阶段期间刷新。 在第一阶段，由于Cj和Cw电容的串联组合，MOS晶体管的漏极或源极的有效寄生贡献较低。 在另一个实施例中，大电阻提供从参考电压到MOS晶体管本体的路径，从而导致Cj和Cw的串联组合的有效寄生电容。 有利地，寄生电容以及其非线性效应降低，操作速度提高以及信号失真和噪声。
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3.发明授权Fast, efficient reference networks for providing low-impedance reference signals to signal processing systems 有权快速，高效的参考网络，用于向信号处理系统提供低阻抗参考信号公开(公告)号：US07830288B2
公开(公告)日：2010-11-09
申请号：US12692967
申请日：2010-01-25
IPC分类号： H03M1/00
摘要： Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of at least one output transistor, a diode-coupled transistor coupled to the output transistor, and a controller. The controller is configured to provide a backgate voltage to the diode-coupled transistor to thereby establish a substantially-constant output current. The controller is further configured to provide a gate voltage to the output transistor to establish a reference voltage.
摘要翻译： 参考网络实施例被提供用于流水线信号转换器系统。 网络实施例是快速和功率有效的，并且它们通过使用至少一个输出晶体管，耦合到输出晶体管的二极管耦合晶体管和控制器来产生低阻抗参考信号。 控制器被配置为向二极管耦合晶体管提供背栅电压，从而建立基本上恒定的输出电流。 控制器还被配置为向输出晶体管提供栅极电压以建立参考电压。
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4.发明授权Residue generators for reduction of charge injection in pipelined converter systems 有权用于减少流水线转换器系统中的电荷注入的残渣发生器公开(公告)号：US07728752B2
公开(公告)日：2010-06-01
申请号：US12291262
申请日：2008-11-05
IPC分类号： H03M1/38
CPC分类号： H03M1/0863 , H03M1/164 , H03M1/442
摘要： Pipelined converter systems include a plurality of converter stages in which some stages generate and pass a residue signal to a succeeding stage for further conversion. The generation of the residue signal can inject spurious charges into a reference source that is used in the generation. The spurious charges reduce the accuracy of the residue signal and the accuracy of the system. Residue generator embodiments are thereby formed to provide reduction charges to the reference source that are arranged to oppose and reduce the spurious charges. This reduction of spurious charges significantly enhances system accuracy and linearity.
摘要翻译： 流水线转换器系统包括多个转换器级，其中一些级产生残余信号并将其传递到后一级用于进一步转换。 残留信号的产生可以将杂散电荷注入到在生成中使用的参考源中。 杂散电荷降低了残留信号的准确度和系统的精度。 由此形成残留发生器实施例，以向参考源提供被布置为反对并减少杂散电荷的减少电荷。 这种减少杂散电荷显着提高了系统的精度和线性。
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5.发明授权公开(公告)号：US07414564B1
公开(公告)日：2008-08-19
申请号：US11820298
申请日：2007-06-18
IPC分类号： H03M1/38
CPC分类号： H03M1/0607 , H03M1/0695 , H03M1/44
摘要： Converter systems are provided which complement sample capacitors in at least one converter stage with replica capacitors. The replica capacitors are switched to receive replica charges from the analog input signal during the same operational mode in which the sample capacitors receive undesirable remnant charges. In an initial portion of a subsequent operational mode, the remnant capacitors are briefly switched to the sample capacitors to substantially cancel the remnant charges. The sample capacitors then participate in obtaining input-signal samples during the remainder of the subsequent operational mode. Because the remnant charges have been substantially canceled, the accuracy of the subsequent operational mode is considerably enhanced. In another system embodiment, the replica capacitor is replaced by a discharge switch which provides a discharge path in an initial portion of the subsequent operational mode.
摘要翻译： 提供了转换器系统，其在具有复制电容器的至少一个转换器级中补充采样电容器。 在相同的操作模式下，复制电容器被切换以从模拟输入信号接收副本电荷，其中采样电容器接收不期望的剩余电荷。 在随后的操作模式的初始部分中，剩余电容器被短暂切换到采样电容器以基本上消除剩余电荷。 然后，采样电容器在随后的操作模式的剩余时间期间参与获得输入信号采样。 由于剩余费用已经被大幅度取消，所以后续操作模式的准确性显着提高。 在另一系统实施例中，复制电容器由放电开关代替，该放电开关在后续操作模式的初始部分提供放电路径。
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6.发明授权Correlation-based background calibration for reducing inter-stage gain error and non-linearity in pipelined analog-to-digital converters 有权基于相关性的背景校准，用于降低流水线模数转换器中的级间增益误差和非线性度公开(公告)号：US08723707B2
公开(公告)日：2014-05-13
申请号：US13560226
申请日：2012-07-27
IPC分类号： H03M1/10
CPC分类号： H03M1/1057 , H03M1/0673 , H03M1/167
摘要： A method and a corresponding device for calibrating a pipelined analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into one of a flash component and a multiplying digital-to-analog converter (MDAC) in at least one stage in the ADC. For each stage of the at least one stage a correlation procedure is performed to estimate, based on an output of the ADC, an amount of gain experienced by the injected dither after propagating through the stage. The stage is then calibrated based on its respective gain estimate.
摘要翻译： 用于校准流水线模数转换器（ADC）的方法和相应的装置包括在至少一级中将随机确定量的抖动注入到闪存组件和乘法数模转换器（MDAC）之一中 在ADC中。 对于至少一个级的每个级，执行相关程序以基于ADC的输出来估计在通过级传播之后所注入的抖动所经历的增益的量。 然后基于其相应的增益估计来校准该级。
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公开(公告)号：US20130120175A1
公开(公告)日：2013-05-16
申请号：US13596626
申请日：2012-08-28
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/1215
摘要： A method and a corresponding device for calibrating an interleaved analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into at least one of a flash component and a multiplying digital-to-analog converter (MDAC) in a selected channel in the ADC. A correlation procedure is performed to estimate, based on an overall ADC output, a gain experienced by the injected dither after propagating through the channel. The injection and the correlation procedure are repeated on at least one additional channel to estimate a gain for each at least one additional channel. The estimated gains of the selected channel and the at least one additional channel are then compared to determine a degree of mismatch between the selected channel and each at least one additional channel. At least one channel is calibrated as a function of the determined degree of mismatch.
摘要翻译： 用于校准交错模数转换器（ADC）的方法和相应的装置包括将随机确定量的抖动注入所选择的闪存组件和乘法数模转换器（MDAC）中的至少一个中 ADC中的通道。 执行相关程序以基于总体ADC输出来估计在通过通道传播之后所注入的抖动所经历的增益。 在至少一个附加信道上重复注入和相关过程以估计每个至少一个附加信道的增益。 然后比较所选择的信道和至少一个附加信道的估计增益，以确定所选择的信道与每个至少一个附加信道之间的失配程度。 至少一个通道被校准为确定的失配程度的函数。
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8.发明申请METHOD AND DEVICE FOR REDUCING INTER-CHANNEL COUPLING IN INTERLEAVED AND MULTI-CHANNEL ADCs 有权用于减少交叉和多通道ADC中的通道间耦合的方法和装置公开(公告)号：US20130120172A1
公开(公告)日：2013-05-16
申请号：US13348795
申请日：2012-01-12
CPC分类号： H03M1/08 , H03M1/1225 , H03M1/167
摘要： A method and a corresponding device for reducing inter-channel coupling in a circuit having a plurality of channels includes injecting a randomly determined amount of dither into a first channel of a circuit having a plurality of channels, and after injecting the dither, obtaining an output signal of a second channel in the plurality of channels. A correlation value indicating a degree of correlation between the injected dither and the output signal is determined, and an amount of charge applied to the second channel due to cross-coupling with the first channel is reduced. The amount of the reduction is calculated as a function of the correlation value.
摘要翻译： 一种用于减少具有多个信道的电路中的信道间耦合的方法和对应装置包括将随机确定的抖动量注入到具有多个信道的电路的第一信道中，并且在注入抖动之后，获得输出 在多个信道中的第二信道的信号。 确定指示注入的抖动与输出信号之间的相关程度的相关值，并且由于与第一通道交叉耦合而施加到第二通道的电荷量减少。 作为相关值的函数计算还原量。
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9.发明授权Correlation-based background calibration of pipelined converters with reduced power penalty 有权流水线转换器的相关性背景校准降低了功率损失公开(公告)号：US07786910B2
公开(公告)日：2010-08-31
申请号：US12228455
申请日：2008-08-12
IPC分类号： H03M1/20
CPC分类号： H03M1/0663 , H03M1/0614 , H03M1/0641 , H03M1/0673 , H03M1/1014 , H03M1/164
摘要： A device and method for correlation-based background calibration of pipelined converters with a reduced power penalty. A pipelined analog-to-digital converter (ADC) utilizes a random or pseudorandom signal to reduce the quantization error of subconverting stages. Stages within the ADC comprise an injection circuit having a plurality of capacitive branches in parallel. Less than all of the branches can function during a given clock cycle of the ADC. This allows a subconverting stage within the ADC to be accurately trimmed before operation using a large amplitude signal. At the same time, the capability to inject smaller amplitude random or pseudorandom signals into the subconverting stage during operation is maintained, saving valuable dynamic range and power. The various capacitive branches are cycled through either randomly or in sequence such that the quantizer manifests the same average gain error over time for which the quantizer was initially trimmed.
摘要翻译： 一种降低功率损失的流水线转换器的基于相关的背景校准的装置和方法。 流水线模数转换器（ADC）利用随机或伪随机信号来减少次转换级的量化误差。 ADC内的阶段包括具有并联的多个电容分支的注入电路。 在ADC的给定时钟周期内，小于所有分支的功能。 这允许在使用大幅度信号的操作之前，ADC内的子转换级被精确地修整。 同时，维持在操作期间将更小幅度的随机或伪随机信号注入子转换级的能力，从而节省宝贵的动态范围和功率。 各种电容分支通过随机或顺序循环使得量化器显示与量化器初始修整的时间相同的平均增益误差。
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10.发明申请Amplifier networks with controlled common-mode level and converter systems for use therewith 有权具有受控共模电平的放大器网络和与其一起使用的转换器系统公开(公告)号：US20100019946A1
公开(公告)日：2010-01-28
申请号：US12220558
申请日：2008-07-25
IPC分类号： H03F3/45
CPC分类号： H03F3/45286 , H03F3/45802 , H03F3/45807 , H03F2203/45101 , H03F2203/45418 , H03F2203/45424 , H03F2203/45434 , H03F2203/45512 , H03F2203/45514 , H03F2203/45642 , H03F2203/45681 , H03F2203/45722
摘要： Effective control of the common-mode level of amplifiers is obtained through control structures (both closed-loop and open-loop structures) which are directed to various amplifier functions such as the reduction of amplifier loading, accurate sensing of common-mode levels, mitigation of headroom restraints, and proper transistor biasing. This common-mode control is especially useful in multiplying analog-to-digital converters (MDACs) of signal processing systems.
摘要翻译： 通过控制结构（闭环和开环结构）获得对放大器共模电平的有效控制，这些控制结构涉及各种放大器功能，例如放大器负载的减小，共模电平的精确检测，缓解 的余量约束，以及适当的晶体管偏置。 这种共模控制在乘法信号处理系统的模数转换器（MDAC）中特别有用。
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