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公开(公告)号：US12073114B2
公开(公告)日：2024-08-27
申请号：US17491058
申请日：2021-09-30
发明人： Hideki Kanayama , Eric M. Scott
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0622 , G06F3/0635 , G06F3/0679
摘要： A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.
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公开(公告)号：US11995008B2
公开(公告)日：2024-05-28
申请号：US17354806
申请日：2021-06-22
IPC分类号： G06F13/16 , G11C11/4063
CPC分类号： G06F13/1642 , G11C11/4063
摘要： A memory controller includes a command queue having an input for receiving memory access commands for a memory channel, and a number of entries for holding a predetermined number of memory access commands, and an arbiter that selects memory commands from the command queue for dispatch to one of a persistent memory and a DRAM memory coupled to the memory channel. The arbiter includes a first-tier sub-arbiter circuit coupled to the command queue for selecting candidate commands from among DRAM commands and persistent memory commands, and a second-tier sub-arbiter circuit coupled to the first-tier sub-arbiter circuit for receiving the candidate commands and selecting at least one command from among the candidate commands.
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公开(公告)号：US11934251B2
公开(公告)日：2024-03-19
申请号：US17219407
申请日：2021-03-31
IPC分类号： G06F1/32 , G06F1/08 , G06F1/3225 , G06F1/3234 , G06F1/3287 , G06F3/06
CPC分类号： G06F1/3275 , G06F1/08 , G06F1/3225 , G06F1/3287 , G06F3/0625 , G06F3/0634 , G06F3/0658 , G06F3/0679
摘要： A memory controller couples to a data fabric clock domain, and to a physical layer interface circuit PHY clock domain. A first interface circuit adapts transfers between the data fabric clock domain (FCLK) and the memory controllers clock domain, and a second interface circuit couples the memory controller to the PHY clock domain. A power controller responds to a power state change request by sending commands to the second interface circuit to change parameters of a memory system and to update a set of timing parameters of the memory controller according to a selected power state of a plurality of power states. The power controller further responds to a request to synchronize with a new frequency on the FCLK domain by changing a set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.
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公开(公告)号：US11886368B2
公开(公告)日：2024-01-30
申请号：US17657655
申请日：2022-04-01
发明人： Athar Ali Khan P , Saravanan Ganesh
CPC分类号： G06F13/385 , G06F13/4068 , G06F13/4282 , H03K5/14 , H03K5/15006 , G06F2213/0042
摘要： A repeater circuit includes at least a first input, and output, and a repeater. The first input for receiving a single-ended data signal from an embedded universal serial bus (eUSB) host. The output provides a differential data signal in a differential universal serial bus (USB) format. The repeater is coupled between the first input and output for converting the single-ended data signal to a differential data signal, the repeater includes an adaptive delay element operable for both sides of the differential data signal to delay one, but not both, of a rising edge and a falling edge of the differential data signal in order to meet a crossover specification for the USB format.
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5.发明授权公开(公告)号：US11885874B2
公开(公告)日：2024-01-30
申请号：US16378722
申请日：2019-04-09
发明人： Marek Hustava , Tomas Suchy
CPC分类号： G01S15/10 , G01S7/524 , G01S7/527 , G01S7/52026
摘要： In one form, an acoustic distance measuring circuit includes a frequency generator, a transmitter amplifier, an acoustic transducer, and a sensing circuit. The sensing circuit includes an input adapted to be coupled to the acoustic transducer, for receiving an input signal. The sensing circuit provides an in-phase portion and a quadrature portion of the input signal to a filter. The sensing circuit filters the in-phase portion and the quadrature portion and calculates a phase of the input signal in response to the filtered in-phase and quadrature portions. The sensing circuit determines a frequency slope of the input signal in response to calculating the phase and provides the frequency slope of the input signal to an output.
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公开(公告)号：US11797369B2
公开(公告)日：2023-10-24
申请号：US17864804
申请日：2022-07-14
CPC分类号： G06F11/0772 , G06F3/0679 , G06F11/073 , G06F11/141
摘要： A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.
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公开(公告)号：US11755477B2
公开(公告)日：2023-09-12
申请号：US17563675
申请日：2021-12-28
IPC分类号： G06F12/00 , G06F12/0802
CPC分类号： G06F12/0802 , G06F2212/604
摘要： A cache includes an upstream port, a downstream port, a cache memory, and a control circuit. The control circuit temporarily stores memory access requests received from the upstream port, and checks for dependencies for a new memory access request with older memory access requests temporarily stored therein. If one of the older memory access requests creates a false dependency with the new memory access request, the control circuit drops an allocation of a cache line to the cache memory for the older memory access request while continuing to process the new memory access request.
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公开(公告)号：US11742857B2
公开(公告)日：2023-08-29
申请号：US17810745
申请日：2022-07-05
发明人： Alexander Heubi
IPC分类号： H03K19/01 , H03K19/0185 , H03K3/037 , H03K19/20
CPC分类号： H03K19/018521 , H03K3/037 , H03K19/20
摘要： A level shifter circuit shifts a digital signal between first and second voltage levels. For a LOW to HIGH transition, an output PMOS transistor is switched on using a first NMOS transistor activated by the digital signal at the first voltage level while a second NMOS transistor is switched off to uncouple the output PMOS transistor from ground, and a third NMOS transistor is switched off to uncouple a current mirror circuit from ground. For a HIGH to LOW transition, the output PMOS transistor is switched off and a fourth NMOS transistor is switched on using an output of the current mirror circuit. The second NMOS transistor is switched on using an inverted version of the digital signal, and the current in the current mirror circuit is turned off with a fifth NMOS transistor when the drain of the output PMOS transistor approaches the voltage level of ground.
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公开(公告)号：US11705901B2
公开(公告)日：2023-07-18
申请号：US17805916
申请日：2022-06-08
发明人： Alexander Heubi
IPC分类号： H03K19/0185 , H03K17/16
CPC分类号： H03K17/161 , H03K19/018521
摘要： A driver circuit drives an output terminal with an input/output voltage using an NMOS transistor and a PMOS transistor. A pre-driver for the NMOS transistor supplied with a drive voltage and receives a data signal referenced to the drive voltage. A pre-driver for the PMOS transistor has a positive supply input connected to the positive supply rail, a negative supply input receiving a second drive voltage equal to the supply voltage minus the drive voltage. A level shifter circuit, shifts the data signal to be referenced between the supply voltage and the second drive voltage. A charge pump circuit for providing second drive voltage, the charge pump circuit driven with a variable switching frequency proportional to a current of the PMOS transistor.
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公开(公告)号：US11693813B2
公开(公告)日：2023-07-04
申请号：US16427020
申请日：2019-05-30
CPC分类号： G06F13/4282 , G06F13/1689 , G06F2213/0026
摘要： A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.
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