High-precision impedance measurement device

    公开(公告)号:US11899073B2

    公开(公告)日:2024-02-13

    申请号:US17435027

    申请日:2020-09-22

    CPC classification number: G01R31/389 H03F3/04

    Abstract: An impedance measurement device of the present disclosure includes: an electrochemical energy device; an amplifier connected to each connection terminal of the electrochemical energy device and configured to amplify a signal introduced into a wiring; and a main board configured to receive the signal from the amplifier and measure an impedance. Accordingly, the present invention has advantages in that high resistance to electromagnetic interference may be achieved by disposing a preamplifier close to a terminal of an electrochemical energy device to amplify only the signal without amplifying a noise introduced into a wiring.

    Variable gain amplifier and sampler offset calibration without clock recovery

    公开(公告)号:US11627022B2

    公开(公告)日:2023-04-11

    申请号:US17684268

    申请日:2022-03-01

    Inventor: Ali Hormati

    Abstract: Methods and systems are described for generating a time-varying information signal at an output of a variable gain amplifier (VGA), sampling, using a sampler having a vertical decision threshold associated with a target signal amplitude, the time-varying information signal asynchronously to generate a sequence of decisions from varying sampling instants in sequential signaling intervals, the sequence of decisions comprising (i) positive decisions indicating the time-varying information signal is above the target signal amplitude and (ii) negative decisions indicating the time-varying information signal is below the target signal amplitude, accumulating a ratio of positive decisions to negative decisions, and generating a gain feedback control signal to adjust a gain setting of the VGA responsive to a mismatch of the accumulated ratio with respect to a target ratio.

    Dynamic integration time adjustment of a clocked data sampler using a static analog calibration circuit

    公开(公告)号:US11515885B2

    公开(公告)日:2022-11-29

    申请号:US17347589

    申请日:2021-06-15

    Applicant: Kandou Labs SA

    Abstract: Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.

    High speed communications system
    8.
    发明授权

    公开(公告)号:US11483187B2

    公开(公告)日:2022-10-25

    申请号:US17468405

    申请日:2021-09-07

    Applicant: Kandou Labs SA

    Abstract: Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.

    Frame-rate up conversion with low complexity

    公开(公告)号:US11470344B2

    公开(公告)日:2022-10-11

    申请号:US16965571

    申请日:2019-01-28

    Abstract: Systems and methods are described for selecting a motion vector (MV) to use in frame-rate up conversion (FRUC) coding of a block of video. In one embodiment, a first set of motion vector candidates is identified for FRUC prediction of the block. A search center is defined based on the first set of motion vector candidates, and a search window is determined, the search window having a selected width and being centered on the search center. A search for a selected MV is performed within the search window. In some embodiments, an initial set of MVs is processed with a clustering algorithm to generate a smaller number of MVs that are used as the first set. The selected MV may be subject to a motion refinement search, which may also be performed over a constrained search range. In additional embodiments, search iterations are constrained to limit complexity.

    Clock and data recovery lock detection circuit for verifying lock condition in presence of imbalanced early to late vote ratios

    公开(公告)号:US11463092B1

    公开(公告)日:2022-10-04

    申请号:US17220786

    申请日:2021-04-01

    Applicant: Kandou Labs SA

    Abstract: Methods and systems are described for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote measurements, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.

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