公开(公告)号：US12130769B2

公开(公告)日：2024-10-29

申请号：US18073327

申请日：2022-12-01

申请人： XILINX, INC.

发明人： David P. Schultz ,  Richard W. Swanson

IPC分类号： G06F13/42

CPC分类号： G06F13/4291 ,  G06F2213/0016

摘要： An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. A frequency of the interface clock signal is a multiple of a frequency of the logic clock signal.

公开(公告)号：US12111784B2

公开(公告)日：2024-10-08

申请号：US17959903

申请日：2022-10-04

申请人： XILINX, INC.

发明人： Krishnan Srinivasan ,  Abbas Morshed ,  Sagheer Ahmad

IPC分类号： G06F13/40

CPC分类号： G06F13/4059 ,  G06F13/4022

摘要： Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.

公开(公告)号：US20240333307A1

公开(公告)日：2024-10-03

申请号：US18128943

申请日：2023-03-30

申请人： XILINX, INC. ,  Advanced Micro Devices, Inc.

发明人： Kumar RAHUL ,  John J. WUU ,  Santosh YACHARENI

IPC分类号： H03M13/11 ,  H03M13/00

CPC分类号： H03M13/1174 ,  H03M13/616

摘要： An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.

公开(公告)号：US20240330216A1

公开(公告)日：2024-10-03

申请号：US18193129

申请日：2023-03-30

申请人： Xilinx, Inc.

发明人： Chandrasekhar S. Thyamagondlu ,  Nicholas Trank

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F2213/28

摘要： A direct memory access (DMA) system includes a plurality of read circuits and a switch coupled to a plurality of data port controllers configured to communicate with one or more data processing systems. The DMA system includes a read scheduler circuit coupled to the plurality of read circuits and the switch. The read scheduler circuit is configured to receive read requests from the plurality of read circuits, request allocation of entries of a data memory for the read requests, and submit the read requests to the one more data processing systems via the switch. The DMA system includes a read reassembly circuit coupled to the plurality of read circuits, the switch, and the read scheduler circuit. The read reassembly circuit is configured to reorder read completion data received from the switch for the read requests and provide read completion data, as reordered, to the plurality of read circuits.

公开(公告)号：US20240330145A1

公开(公告)日：2024-10-03

申请号：US18193488

申请日：2023-03-30

申请人： Xilinx, Inc.

发明人： Elessar Taggart ,  Ishita Ghosh ,  Rishi Bharadwaj Subramanian

IPC分类号： G06F11/34

CPC分类号： G06F11/348 ,  G06F11/3476

摘要： An integrated circuit includes a high-speed debug port trace circuit. The high-speed debug trace circuit includes a plurality of input receiver circuits each configured to receive a stream of trace data. The plurality of input receiver circuits receive streams of trace data from a plurality of compute circuits of different compute circuit types. The plurality of compute circuits are within the integrated circuit. The high-speed debug trace circuit includes a stream selector circuit configured to perform multiple stages of arbitration among the plurality of streams of trace data to generate output trace data. The stream selector circuit inserts compute circuit type identifiers within the output trace data. Each compute circuit type identifier specifies a compute circuit type that originated each portion of trace data of the output trace data. The high-speed debug trace circuit includes an output transmitter circuit configured to output the output trace data.

公开(公告)号：US20240328851A1

公开(公告)日：2024-10-03

申请号：US18128397

申请日：2023-03-30

申请人： XILINX, INC.

发明人： Zhaowen WANG ,  Mayank RAJ

IPC分类号： G01J1/44

CPC分类号： G01J1/44 ,  G01J2001/446

摘要： An integrated circuit (IC) device includes a controller circuitry having an input connected to a photodiode of an optoelectronic circuitry and an output connected to a biasing circuitry, the biasing circuitry having an input connected to the output of the controller circuitry, the controller circuitry configured to transmit a transimpedance control signal code to the biasing circuitry configured to cause the biasing circuitry to offset a DC current component of the output of the photodiode.

公开(公告)号：US12104949B1

公开(公告)日：2024-10-01

申请号：US18128397

申请日：2023-03-30

申请人： XILINX, INC.

发明人： Zhaowen Wang ,  Mayank Raj

IPC分类号： G01J1/44

CPC分类号： G01J1/44 ,  G01J2001/446

摘要： An integrated circuit (IC) device includes a controller circuitry having an input connected to a photodiode of an optoelectronic circuitry and an output connected to a biasing circuitry, the biasing circuitry having an input connected to the output of the controller circuitry, the controller circuitry configured to transmit a transimpedance control signal code to the biasing circuitry configured to cause the biasing circuitry to offset a DC current component of the output of the photodiode.

公开(公告)号：US20240314107A1

公开(公告)日：2024-09-19

申请号：US18185634

申请日：2023-03-17

申请人： Xilinx, Inc.

发明人： Chandrasekhar S. Thyamagondlu ,  Akhil Krishnan ,  Darren Jue

IPC分类号： H04L9/40 ,  G06F13/40

CPC分类号： H04L63/0245 ,  G06F13/4027 ,  H04L63/0209

摘要： Handling port resets in a multi-port system includes monitoring, using a plurality of firewall circuits, a plurality of controllers corresponding to different communication ports for a reset condition. The plurality of controllers are coupled to a direct memory access (DMA) system through a plurality of bridge circuits. A selected firewall circuit detects a reset condition on a selected controller coupled thereto. The selected controller is coupled to a selected bridge circuit of the plurality of bridge circuits. In response to detecting the reset condition, the selected firewall circuit implements a firewall operating mode. While operating in the firewall operating mode, the selected firewall circuit is configured to control operation of the selected bridge circuit thereby isolating the selected controller from the DMA system. Firewall operating mode of firewall circuits also may be initiated by a management processor in a proactive manner.

公开(公告)号：US20240313781A1

公开(公告)日：2024-09-19

申请号：US18123160

申请日：2023-03-17

申请人： XILINX, INC.

发明人： Brian C. GAIDE ,  Sagheer AHMAD ,  Trevor J. BAUER ,  Kenneth MA ,  David P. SCHULTZ ,  John O'DWYER ,  Richard W. SWANSON ,  Bhuvanachandran K. NAIR ,  Millind MITTAL

IPC分类号： H03K19/17736 ,  G01R31/317 ,  H03K19/0175 ,  H03K19/17796

CPC分类号： H03K19/17744 ,  G01R31/31701 ,  H03K19/017581 ,  H03K19/17796

摘要： Embodiments herein describe connecting an ASIC to another integrated circuit (or die) using inter-die connections. In one embodiment, an ASIC includes a fabric sliver (e.g., a small region of programmable logic circuitry). Inter-die fabric extension connections are used to connect the fabric sliver in the ASIC to fabric (e.g., programmable logic) in the other integrated circuit. These connections effectively extend the fabric in the ASIC to include the fabric in the other integrated circuit. Hardened IP blocks in the ASIC can then use the fabric sliver and the inter-die extension connections to access computer resources in the other integrated circuit.

公开(公告)号：US20240281325A1

公开(公告)日：2024-08-22

申请号：US18111805

申请日：2023-02-20

申请人： XILINX, INC.

发明人： Ygal ARBEL ,  Jonathan JASPER ,  Abbas MORSHED

IPC分类号： G06F11/10 ,  G06F12/0871 ,  G06F12/0891

CPC分类号： G06F11/1068 ,  G06F12/0871 ,  G06F12/0891

摘要： An integrated circuit (IC) device includes processor circuitry configured to output a first memory command having a first memory address, and in-line error correction control (ILECC) circuitry configured to receive the first memory command and output the first memory command to a memory device. The ILECC circuitry includes an error correction code (ECC) cache configured to store a first local ECC associated with the first memory command in a first cache line.