- 专利标题: FIREWALLING COMMUNICATION PORTS IN A MULTI-PORT SYSTEM
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申请号: US18185634申请日: 2023-03-17
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公开(公告)号: US20240314107A1公开(公告)日: 2024-09-19
- 发明人: Chandrasekhar S. Thyamagondlu , Akhil Krishnan , Darren Jue
- 申请人: Xilinx, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Xilinx, Inc.
- 当前专利权人: Xilinx, Inc.
- 当前专利权人地址: US CA San Jose
- 主分类号: H04L9/40
- IPC分类号: H04L9/40 ; G06F13/40
摘要:
Handling port resets in a multi-port system includes monitoring, using a plurality of firewall circuits, a plurality of controllers corresponding to different communication ports for a reset condition. The plurality of controllers are coupled to a direct memory access (DMA) system through a plurality of bridge circuits. A selected firewall circuit detects a reset condition on a selected controller coupled thereto. The selected controller is coupled to a selected bridge circuit of the plurality of bridge circuits. In response to detecting the reset condition, the selected firewall circuit implements a firewall operating mode. While operating in the firewall operating mode, the selected firewall circuit is configured to control operation of the selected bridge circuit thereby isolating the selected controller from the DMA system. Firewall operating mode of firewall circuits also may be initiated by a management processor in a proactive manner.
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