公开(公告)号：US12019576B2

公开(公告)日：2024-06-25

申请号：US17879675

申请日：2022-08-02

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Ygal Arbel ,  Sagheer Ahmad ,  Abbas Morshed

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F2213/40

Abstract: Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.

公开(公告)号：US11892966B2

公开(公告)日：2024-02-06

申请号：US17551132

申请日：2021-12-14

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Ygal Arbel ,  Sagheer Ahmad

IPC: G06F13/36 ,  G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0016

Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

公开(公告)号：US12235782B2

公开(公告)日：2025-02-25

申请号：US18086531

申请日：2022-12-21

Applicant: XILINX, INC.

Inventor： Aman Gupta ,  Krishnan Srinivasan ,  Ahmad R. Ansari ,  Sagheer Ahmad

IPC: G06F13/40 ,  G06F12/1009

Abstract: Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.

公开(公告)号：US12019908B2

公开(公告)日：2024-06-25

申请号：US17389272

申请日：2021-07-29

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Shishir Kumar ,  Sagheer Ahmad ,  Abbas Morshed ,  Aman Gupta

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0679

Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

公开(公告)号：US11983264B2

公开(公告)日：2024-05-14

申请号：US17457839

申请日：2021-12-06

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  Aman Gupta ,  Krishnan Srinivasan ,  Sagheer Ahmad

IPC: G06F21/54 ,  G06F21/62 ,  G06F21/85

CPC classification number: G06F21/54 ,  G06F21/6209 ,  G06F21/85

Abstract: Embodiments herein describe offloading encryption activities to a network interface controller/card (NIC) (e.g., a SmartNIC) which frees up server compute resources to focus on executing customer applications. In one embodiment, the smart NIC includes a system on a chip (SoC) implemented on an integrated circuit (IC) that includes an embedded processor. Instead of executing a transport layer security (TLS) stack entirely in the embedded processor, the embodiments herein offload certain TLS tasks to a Public Key Infrastructure (PKI) accelerator such as generating public-private key pairs.

公开(公告)号：US20240211138A1

公开(公告)日：2024-06-27

申请号：US18145339

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Aman Gupta ,  Krishnan Srinivasan ,  Shishir Kumar ,  Sagheer Ahmad ,  Ahmad R. Ansari

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0673

Abstract: A system includes a plurality of processing elements and a plurality of memory controllers. The system includes a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers. The NoC includes a sparse network coupled to the plurality of processing elements and a non-blocking network coupled to the sparse network and the plurality of memory controllers. The plurality of processing elements execute a plurality of applications. Each application has a same deterministic memory access performance in accessing associated ones of the plurality of memory controllers via the sparse network and the non-blocking network of the NoC.

公开(公告)号：US11985061B1

公开(公告)日：2024-05-14

申请号：US17227258

申请日：2021-04-09

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Abbas Morshed ,  Aman Gupta ,  Sagheer Ahmad

IPC: H04L45/302 ,  G06F15/78 ,  H04L45/00 ,  H04L45/42 ,  H04L45/745

CPC classification number: H04L45/302 ,  G06F15/7825 ,  H04L45/42 ,  H04L45/566 ,  H04L45/745 ,  H04L45/34

Abstract: Embodiments herein describe an integrated circuit that includes a network on chip (NoC) where an egress logic block or switch performs a route lookup for a subsequent (e.g., downstream) switch in the NoC (referred to herein as look-ahead routing). After receiving the packet and a port ID from the egress logic block or the switch, the downstream switch knows, without performing route lookup of its own, on which port it should forward the packet. Thus, if the downstream switch performs other functions that are dependent on knowing the destination port (e.g., arbitration or QoS updating), the downstream switch can perform those functions immediately since the port ID was already determined by, and received from, the previous network element.

公开(公告)号：US11636061B2

公开(公告)日：2023-04-25

申请号：US17464642

申请日：2021-09-01

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Sagheer Ahmad ,  Ygal Arbel

IPC: G06F13/42 ,  G06F13/40

Abstract: Embodiments herein describe on-demand packetization where data that is too large to be converted directly into data words (DWs) for a chip-to-chip (C2C) interface are packetized instead. When identifying a protocol word that is larger than the DW of the C2C interface, a protocol layer can perform packetization where a plurality of protocol words are packetized and sent as a transfer. In one embodiment, the protocol layer removes some or all of the control data or signals in the protocol words so that the protocol words no longer exceed the size of the DW. These shortened protocol words can then be mapped to DWs and transmitted as separate packets on the C2C. The protocol layer can then collect the portion of the control data that was removed from the protocol words and transmit this data as a separate packet on the C2C interface.

公开(公告)号：US12111784B2

公开(公告)日：2024-10-08

申请号：US17959903

申请日：2022-10-04

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Abbas Morshed ,  Sagheer Ahmad

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/4022

Abstract: Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.

公开(公告)号：US12066969B2

公开(公告)日：2024-08-20

申请号：US17589633

申请日：2022-01-31

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Sagheer Ahmad ,  Ygal Arbel ,  Millind Mittal

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/42 ,  G06F13/382 ,  G06F13/4063

Abstract: Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.