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公开(公告)号：US11914409B2
公开(公告)日：2024-02-27
申请号：US17564947
申请日：2021-12-29
Applicant: SILEGO TECHNOLOGY INC.
Inventor： Hua Zhu
Abstract: Disclosed is an integrated user programmable slew-rate controlled soft-start for a low-dropout regulator that includes a current steering stage and an integrator stage. The current steering stage may also be denoted as an error amplifier. A Miller compensation capacitor couples between an input node to the integrator stage and an output node for an output voltage of LDO. During a power up period of the LDO, the current steering stage generates an input current that charges the Miller compensation capacitor. This controlled charging of the Miller compensation capacitor controls the slew rate of the output voltage as it rises to its regulated value at a completion of the power up period.
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公开(公告)号：US20230335511A1
公开(公告)日：2023-10-19
申请号：US18340366
申请日：2023-06-23
Applicant: Silego Technology Inc.
Inventor： John McDonald , Tom Truong , David Kunteh Chow
IPC: H01L23/64 , H01L23/498
CPC classification number: H01L23/645 , H01L23/49838 , H01L28/10 , H01L23/49894
Abstract: A packaging substrate and a method for mounting an integrated circuit and/or a circuit component is presented. The packaging substrate includes an upper surface for mounting the integrated circuit and/or circuit component; a lower surface opposite to the upper surface, wherein the lower surface is for mounting to a printed circuit board (PCB); a non-conductive material; wherein the non-conductive material is a plastic: an inductor structure at least partially embedded in the non-conductive material; first and second conductive materials, and conductive pillars, arranged to form a first coil and a second coil having an inductance; wherein the first coil and second coil are arranged as a toroid transformer wound in a double helix configuration.
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公开(公告)号：US20220103128A1
公开(公告)日：2022-03-31
申请号：US17484069
申请日：2021-09-24
Applicant: Silego Technology Inc.
Inventor： Ambreesh Bhattad , Gary Hague
Abstract: The present document relates to differential amplifiers. A differential amplifier may comprise a current source, a first transistor, a second transistor, and a compensation circuit. A reference voltage may be applied to a first terminal of the first transistor, and a second terminal of the first transistor may be coupled to an output of the current source. A feedback voltage may be applied to a first terminal of the second transistor, and a second terminal of the second transistor may be coupled to the output of the current source. The compensation circuit may comprise a capacitive element coupled to the first terminal of the first transistor, and the compensation circuit may be configured to reduce a change of the reference voltage at the first terminal of the first transistor.
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公开(公告)号：US11165344B2
公开(公告)日：2021-11-02
申请号：US16731721
申请日：2019-12-31
Applicant: SILEGO TECHNOLOGY INC.
Inventor： Kevin Yi Cheng Chang
IPC: H02M3/07
Abstract: Disclosed is an interleaved buck-boost converter. The interleaved buck-boost converter comprises a multi-level direct current (DC) to DC converter (MLDC converter), a flying capacitor monitor, and a voltage-level controller. The MLDC converter includes the IMPM and the IMPM includes the flying capacitor. The flying capacitor monitor is in signal communication with the flying capacitor and the voltage-level controller is in signal communication with the flying capacitor monitor. The flying capacitor monitor compares a flying capacitor voltage of the flying capacitor and switches a state of operation of the MLDC converter if the flying capacitor voltage is less than a first flying capacitor reference voltage.
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公开(公告)号：US20210203223A1
公开(公告)日：2021-07-01
申请号：US16731721
申请日：2019-12-31
Applicant: SILEGO TECHNOLOGY INC.
Inventor： Kevin Yi Cheng Chang
IPC: H02M3/07
Abstract: Disclosed is an interleaved buck-boost converter. The interleaved buck-boost converter comprises a multi-level direct current (DC) to DC converter (MLDC converter), a flying capacitor monitor, and a voltage-level controller. The MLDC converter includes the IMPM and the IMPM includes the flying capacitor. The flying capacitor monitor is in signal communication with the flying capacitor and the voltage-level controller is in signal communication with the flying capacitor monitor. The flying capacitor monitor compares a flying capacitor voltage of the flying capacitor and switches a state of operation of the MLDC converter if the flying capacitor voltage is less than a first flying capacitor reference voltage.
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Patent Agency Ranking
公开(公告)号：US10782158B1
公开(公告)日：2020-09-22
申请号：US16138240
申请日：2018-09-21
Applicant: Silego Technology, Inc.
Inventor： Jozef Froniewski
Abstract: A contactless encoder is disclosed. The encoder comprises a selector configured to select one of a plurality of states associated with the encoder. The encoder furthermore comprises an integrated circuit comprising a finite state machine configured to detect a currently selected state by the selector and generate an output signal corresponding to the detected currently selected state, wherein the currently selected state is detected based on a capacitive coupling between the selector and a portion of the encoder associated with the currently selected state.
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公开(公告)号：US09583478B1
公开(公告)日：2017-02-28
申请号：US13089194
申请日：2011-04-18
Applicant: Marcelo A. Martinez
Inventor： Marcelo A. Martinez
IPC: H01L27/02 , H01L23/522 , H01L23/528 , H01L29/417 , H01L25/07
CPC classification number: H01L27/0207 , H01L23/522 , H01L23/5221 , H01L23/5226 , H01L23/5283 , H01L23/5286 , H01L25/072 , H01L29/41758 , H01L2224/49171
Abstract: A lateral power MOSFET structure is disclosed. In some embodiments, a semiconductor device comprises substantially concentric source, channel, and drain regions; a metal layer at least in part comprising a drain plane disposed over the source, channel, and drain regions; and a metal layer at least in part comprising a source plane disposed over the source, channel, and drain regions.
Abstract translation: 公开了横向功率MOSFET结构。 在一些实施例中，半导体器件包括基本上同心的源极，沟道和漏极区域; 至少部分地包括设置在所述源极，沟道和漏极区域上的漏极平面的金属层; 以及至少部分地包括设置在所述源极，沟道和漏极区域上的源极平面的金属层。
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公开(公告)号：US20130063189A1
公开(公告)日：2013-03-14
申请号：US13607498
申请日：2012-09-07
Applicant: Thomas D. Brumett, JR. , Marcelo Martinez , John Othniel McDonald
Inventor： Thomas D. Brumett, JR. , Marcelo Martinez , John Othniel McDonald
IPC: H03K3/00
CPC classification number: H03K3/012 , H03K17/166 , H03K17/687
Abstract: An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.
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公开(公告)号：US20120019287A1
公开(公告)日：2012-01-26
申请号：US13189397
申请日：2011-07-22
Applicant: Thomas D. Brumett, JR. , Marcelo Martinez , John Othniel McDonald
Inventor： Thomas D. Brumett, JR. , Marcelo Martinez , John Othniel McDonald
IPC: H03B1/00
CPC classification number: H03K3/012 , H03K17/166 , H03K17/687
Abstract: An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.
Abstract translation: 公开了一种用于晶体管开关的集成电路。 在一些实施例中，运算放大器被配置为驱动晶体管，并且压摆率控制电路被配置为在导通期间控制晶体管源电压的转换速率。 晶体管源极电压被用作对运算放大器的反馈，以便在晶体管的切换期间促进晶体管源极电压的闭环控制。
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公开(公告)号：US20080204070A1
公开(公告)日：2008-08-28
申请号：US12070374
申请日：2008-02-15
Applicant: Jie Chen , Ting-Yen Chiang , Kuang-Yu Chen , Chen Yu Wang , Joe Froniewski
Inventor： Jie Chen , Ting-Yen Chiang , Kuang-Yu Chen , Chen Yu Wang , Joe Froniewski
IPC: H03K19/0185
CPC classification number: H03K19/018521
Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.
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