公开(公告)号：US07612580B2

公开(公告)日：2009-11-03

申请号：US12070374

申请日：2008-02-15

Applicant: Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

Inventor： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

IPC: H03K19/0175

CPC classification number: H03K19/018521

Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

Abstract translation: 公开了一种用于PC架构的时钟驱动电路和驱动多条输出线的方法。 时钟驱动电路包括一个时钟发生电路，该时钟发生电路耦合到用于PC的输出缓冲器，该输出缓冲器具有连接到具有输出负载阻抗的多个输出负载的多条输出线。 输出线在低于电源电压的输出电压下差分驱动。 该电路包括具有电压节点阻抗的电压节点。 电压节点维持在基本上的输出电压。 该电路包括吸收来自电压节点的电流的电流吸收晶体管。 电流吸收晶体管以由电流吸收晶体管的尺寸确定的欧姆电阻为特征的线性区域工作。 通过调整电流吸收晶体管的尺寸，将电压节点的阻抗与负载阻抗之一相匹配。

公开(公告)号：US07358772B1

公开(公告)日：2008-04-15

申请号：US11069921

申请日：2005-02-28

Applicant: Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

Inventor： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

IPC: H03K19/0175

CPC classification number: H03K19/018521

Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

Abstract translation: 公开了一种用于PC架构的时钟驱动电路和驱动多条输出线的方法。 时钟驱动电路包括一个时钟发生电路，该时钟发生电路耦合到用于PC的输出缓冲器，该输出缓冲器具有连接到具有输出负载阻抗的多个输出负载的多条输出线。 输出线在低于电源电压的输出电压下差分驱动。 该电路包括具有电压节点阻抗的电压节点。 电压节点维持在基本上的输出电压。 该电路包括吸收来自电压节点的电流的电流吸收晶体管。 电流吸收晶体管以由电流吸收晶体管的尺寸确定的欧姆电阻为特征的线性区域工作。 通过调整电流吸收晶体管的尺寸，将电压节点的阻抗与负载阻抗之一相匹配。

公开(公告)号：US20080204070A1

公开(公告)日：2008-08-28

申请号：US12070374

申请日：2008-02-15

Applicant: Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

Inventor： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

IPC: H03K19/0185

CPC classification number: H03K19/018521

Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

公开(公告)号：US08138785B2

公开(公告)日：2012-03-20

申请号：US12586288

申请日：2009-09-18

Applicant: Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

Inventor： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

IPC: H03K19/0175

CPC classification number: H03K19/018521

Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

Abstract translation: 公开了一种用于PC架构的时钟驱动电路和驱动多条输出线的方法。 时钟驱动电路包括一个时钟发生电路，该时钟发生电路耦合到用于PC的输出缓冲器，该输出缓冲器具有连接到具有输出负载阻抗的多个输出负载的多条输出线。 输出线在低于电源电压的输出电压下差分驱动。 该电路包括具有电压节点阻抗的电压节点。 电压节点维持在基本上的输出电压。 该电路包括吸收来自电压节点的电流的电流吸收晶体管。 电流吸收晶体管以由电流吸收晶体管的尺寸确定的欧姆电阻为特征的线性区域工作。 通过调整电流吸收晶体管的尺寸，将电压节点的阻抗与负载阻抗之一相匹配。

公开(公告)号：US20100148817A1

公开(公告)日：2010-06-17

申请号：US12586288

申请日：2009-09-18

Applicant: Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

Inventor： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

IPC: H03K19/003 ,  H03K19/094

CPC classification number: H03K19/018521

Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

Abstract translation: 公开了一种用于PC架构的时钟驱动电路和驱动多条输出线的方法。 时钟驱动电路包括一个时钟发生电路，该时钟发生电路耦合到用于PC的输出缓冲器，该输出缓冲器具有连接到具有输出负载阻抗的多个输出负载的多条输出线。 输出线在低于电源电压的输出电压下差分驱动。 该电路包括具有电压节点阻抗的电压节点。 电压节点维持在基本上的输出电压。 该电路包括吸收来自电压节点的电流的电流吸收晶体管。 电流吸收晶体管以由电流吸收晶体管的尺寸确定的欧姆电阻为特征的线性区域工作。 通过调整电流吸收晶体管的尺寸，将电压节点的阻抗与负载阻抗之一相匹配。