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    PROTECTION OF THE CONTENT OF A FUSE MEMORY
    3.
    发明申请
    PROTECTION OF THE CONTENT OF A FUSE MEMORY 有权

    公开(公告)号：US20250004051A1

    公开(公告)日：2025-01-02

    申请号：US18883619

    申请日：2024-09-12

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Mark Trimmer

    IPC: G01R31/317 ,  G01R31/3185 ,  G06F12/14 ,  G11C29/10

    Abstract: The present disclosure relates to a method wherein a state of an integrated circuit between a first state (e.g., CLOSED), allowing a reading access to the first area of fuse-type non-volatile memory by a processor, and a second state (e.g., OPEN), forbidding the reading access to the memory to the processor, is conditioned to a verification, by a finite state machine, of values of a first fuse word of the memory, representative of a number of transitions to the first state and of a second fuse word of the memory, representative of a number of transitions to the second state.

    USB POWER DELIVERY INTERFACE
    4.
    发明申请
    USB POWER DELIVERY INTERFACE 有权

    公开(公告)号：US20240402778A1

    公开(公告)日：2024-12-05

    申请号：US18798023

    申请日：2024-08-08

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Christophe Lorin ,  Nathalie Ballot

    IPC: G06F1/26 ,  G06F13/40

    Abstract: The present disclosure relates to an USB PD-type interface including a first node receiving a first potential, a second node delivering a second potential, and a third node at a reference potential; a resistor connected between a fourth node coupled to the first node, and a fifth node; a MOS transistor connected between the fifth node and the second node; a bipolar transistor having a collector connected to a gate of the MOS transistor and an emitter connected to the fourth node or the fifth node; and a circuit configured to deliver a control potential to a base of the bipolar transistor determined from a current in the first resistor.

    Mains monitoring
    5.
    发明授权
    Mains monitoring 有权

    公开(公告)号：US12158483B2

    公开(公告)日：2024-12-03

    申请号：US18053974

    申请日：2022-11-09

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Christophe Lorin

    IPC: G01R15/14 ,  G01R1/20 ,  G01R27/14

    Abstract: In accordance with an embodiment, an integrated circuit chip includes a first input configured to receive a rectified potential and a second input configured to receive a reference potential; a first circuit configured to maintain the rectified potential at a constant value on the first input; a second circuit having a power supply input coupled to the first node; a first resistor series-connected to the first circuit between the second input and the first node, or connected between the first input and the first node; a third circuit connected across the first resistor and configured to deliver a signal which is an image of a current in the first resistor; and a fourth circuit configured to determine a mains frequency and/or a mains voltage based at least on the signal which is the image of the current in the first resistor.

    Integrated circuit comprising a non-volatile memory
    6.
    发明授权
    Integrated circuit comprising a non-volatile memory 有权

    公开(公告)号：US12148503B2

    公开(公告)日：2024-11-19

    申请号：US17932694

    申请日：2022-09-16

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Xavier Lecoq

    IPC: G11C7/06 ,  G11C7/04 ,  G11C7/10

    Abstract: In an embodiment an integrated circuit includes a non-volatile memory having a plurality of memory cells, wherein each memory cell is configured to store information, and wherein each memory cell is configured to provide a reading current having an intensity dependent on a value stored in the memory cell when the memory cell is selected for reading; and a sense amplifier including a first amplifier configured to amplify the reading current of each memory cell selected for reading, an oscillation generator configured to generate on basis of the amplified signal a signal having oscillations according to a frequency dependent on the intensity of the current of the amplified signal, a counter configured to count the oscillations of the signal generated by the oscillation generator over at least one given period of time and a digital processing circuit configured to determine a value represented by the amplified signal on basis of the value counted during the at least one given period of time using a lookup table between values countable by the counter and values representable by the amplified signal.

    Reading circuit for a pixel array
    10.
    发明授权
    Reading circuit for a pixel array 有权

    公开(公告)号：US12081888B2

    公开(公告)日：2024-09-03

    申请号：US17660084

    申请日：2022-04-21

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Alexandre Mas ,  Abdessamed Mekki ,  Cedric Tubert

    IPC: H04N25/75 ,  H03M1/12 ,  H03M1/46 ,  H04N25/625 ,  H04N25/677

    CPC classification number: H04N25/75 ,  H03M1/1245 ,  H03M1/46 ,  H04N25/625 ,  H04N25/677

    Abstract: The present disclosure relates to a read-out circuit comprising N inputs configured to be connected to N respective outputs of a pixel array of an image sensor, with N being an integer strictly greater than 1; and N analog-to-digital converters organized in K groups, with K being an integer strictly greater than 1 and strictly less than N, and each having a first input coupled to a respective one of the N inputs and a second input. In each group, the second inputs of the analog-to-digital converters of the group are connected together, electrically decoupled from the second inputs of the analog-to-digital converters of the other groups, and configured to receive a first reference signal that is identical for all the analog-to-digital converters of the group.

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