-
公开(公告)号：US12002682B2
公开(公告)日：2024-06-04
申请号：US17783641
申请日：2020-07-23
发明人： Yanli Li , Yushu Yang , Qiang Wu
IPC分类号： H01L21/308 , H01L21/033 , H01L21/311 , H01L21/3213 , H01L21/768
CPC分类号： H01L21/3086 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/3081 , H01L21/3088 , H01L21/31144 , H01L21/32139 , H01L21/76816
摘要： The present invention disclosures a Tip-to-Tip pattern preparation method, comprising: providing a substrate, and sequentially forming a layer to be etched, a first hard mask layer, a second hard mask layer, a sacrificial layer, a first dielectric layer and a first photoresist layer on the substrate, forming a first patterned photoresist layer which has a first Tip-to-Tip pattern by EUV lithography, and transferring the first Tip-to-Tip pattern to the second hard mask layer by etching; then forming a second patterned photoresist layer which has a second Tip-to-Tip pattern by the EUV lithography, and transferring the second Tip-to-Tip pattern to the second hard mask layer by etching; finally, transferring the first Tip-to-Tip pattern and the second Tip-to-Tip pattern to the layer to be etched. The above method needs only performing the EUV lithography twice to form the small-sized Tip-to-Tip pattern with a period halved, that is, the EUV lithography and etching are used for reducing lithography layers and realizing to form the small-sized Tip-to-Tip pattern with the period halved.
-
公开(公告)号：US11916040B2
公开(公告)日：2024-02-27
申请号：US17418816
申请日：2019-12-04
申请人： SHANGHAI IC R&D CENTER CO., LTD. , Shanghai Integrated Circuit Equipment & Materials Industry Innovation Center Co., Ltd.
发明人： Xinyu Li
CPC分类号： H01L24/83 , H01L24/75 , H01L2224/75102 , H01L2224/83894
摘要： The present invention discloses a bonding cavity structure and a bonding method, the bonding cavity structure comprises an upper carrier and a lower carrier, a gas-flow forming mechanism, which comprises multiple open-close integrated arms, the integrated arms are provided with multiple nozzles facing to wafer bonding surfaces, and the nozzles are switched to gas nozzles or vacuum suction nozzles, a closed space is formed by all the integrated arms closed together with the carriers, all the nozzle located on a side of two wafers are set as the gas nozzles, which blow gas parallel to the wafer bonding surfaces, meanwhile, all the nozzles located on the other side of the two wafers are set as the vacuum suction nozzles, which suck the gas blown from the gas nozzle at corresponding position, a high-speed gas-flow is generated between the two wafers, so as to produce a low pressure of Bernoulli effect, the wafers are not only subjected to thrust forces from backsides, but tension forces between the bonding surfaces are also affected by uniform low pressure, which enhances force uniformity during bonding process, and reduces an impact of particles on the bonding surfaces in the closed space.
-
公开(公告)号：US20230363299A1
公开(公告)日：2023-11-09
申请号：US17786526
申请日：2020-07-23
申请人： Shanghai Integrated Circuit Equipment & Materials Industry Innovation Center Co., Ltd. , SHANGHAI IC R&D CENTER CO., LTD.
发明人： Min ZHONG , Ming LI , Shoumian CHEN , Gaoming FENG
CPC分类号： H10N70/8413 , H10B63/10 , H10B63/20 , H10N70/231 , H10N70/8265 , H10N70/023 , H10N70/066
摘要： The present invention disclosures a phase change memory unit, wherein comprising from bottom to top: a bottom electrode, a heating electrode, a phase change unit and a top electrode, the phase change unit is a longitudinally arranged column, which comprises: a cylindrical selector layer, a circular barrier layer and a circular phase change material layer form inside to outside; wherein, the bottom electrode, the heating electrode and the circular phase change material layer are sequentially connected, and the selector layer is connected to the top electrode. The present invention using trench sidewall deposition or via filling, forming the cylindrical phase change unit which is a circular nested structure, which can improve reliability of a device, greatly reduce volume of a phase change operation area and heat energy required, thus heating efficiency is improved obviously, the power consumption of the device is reduced, and high-density storage is realized.
-
公开(公告)号：US11804553B2
公开(公告)日：2023-10-31
申请号：US17280825
申请日：2019-05-05
发明人： Min Zhong , Shoumian Chen
IPC分类号： H01L29/786 , H01L21/02 , H01L29/66
CPC分类号： H01L29/78696 , H01L21/02417 , H01L29/66742 , H01L29/78618
摘要： A transition metal dichalcogenide transistor, comprising: a gate, a gate dielectric layer and a channel layer from bottom to top, a source/drain region are located on both the sides of the gate dielectric layer, wherein, in a plane paralleled to the channel layer, the length of the channel layer in each direction is greater than the length of the gate dielectric layer, and the length of the gate dielectric layer in each direction is greater than or equal to the length of the gate; wherein, the source/drain region are a first transition metal dichalcogenide with metallic properties, and the channel layer is a second transition metal dichalcogenide with semiconductor properties. The present invention provides a transition metal dichalcogenide transistor and a preparation method thereof, which can solve a problem of excessive contact resistance between a transition metal dichalcogenide transistor channel and a source/drain region and can make the transition metal dichalcogenide transistor compatible with the existing CMOS process.
-
公开(公告)号：US20230157188A1
公开(公告)日：2023-05-18
申请号：US17915137
申请日：2020-12-22
发明人： Ao GUO
CPC分类号： H10N70/8833 , H10B63/34 , H10N70/023 , H10N70/063 , H10N70/253
摘要： The present invention is to provide a RRAM cell, comprising: two transistors which are coupled and resistive switching cells, and the number of the resistive switching cells is n; wherein electrodes of the resistive switching cells are connected in sequence to form a horizontal stack structure, and the same electrode is shared between any two adjacent resistive switching cells, the gates of the two transistors are used for applying different control signals respectively, the sources of the two transistors are connected together and used for applying a source signal jointly, drains of the two transistors are connected to one end of each of electrodes of different resistive switching cells which the number thereof is m in the resistive switching cells which the number thereof is n respectively, and the other ends of the electrodes of the resistive switching cells which the number thereof is n are used for applying different bit signals respectively. According to the present invention. Based on vertical channel transistors and resistance switching cells with a horizontal stacked structure, a 2TnR RRAM is formed in the present invention, which can simultaneously realize binary and multi value storage functions according to different operation timings, and cell area is controllable. It can be used to realize a high-density RRAM array and chip.
-
公开(公告)号：US20220415951A1
公开(公告)日：2022-12-29
申请号：US17775600
申请日：2020-07-23
发明人： Xueqiang GU , Ke LU , Yirui ZHAO
IPC分类号： H01L27/146
摘要： The present invention disclosures an image sensor structure and a formation method thereof, wherein comprising: a pixel unit array, a peripheral circuit set at the periphery of the pixel unit array, and a composite shield structure around the pixel unit array and between the pixel unit array and the peripheral circuit, the composite shield structure comprises a light shield structure and a heat shield structure; wherein, the light shield structure comprises a metal isolation structure around the pixel unit array for isolating light emitted by the peripheral circuit, and the heat shield structure comprises a cavity set inside the metal isolation structure, the cavity is filled with a thermal isolation medium for preventing heat transfer to the pixel unit array. The present invention can avoid image quality deterioration and distortion caused by light and heat of the peripheral circuit of the image sensor.
-
公开(公告)号：US20220262833A1
公开(公告)日：2022-08-18
申请号：US17665536
申请日：2022-02-06
申请人： Shanghai IC R&D Center Co., Ltd. , Shanghai Integrated Circuit Equipment & Materials Industry Innovation Center Co., Ltd.
发明人： Xiaoxu Kang
IPC分类号： H01L27/146
摘要： The present disclosure relates to an image sensor structure and a manufacturing method thereof. A detection structure layer and a blind pixel structure layer are used. The detection structure layer and the blind pixel structure layer are effectively combined and further formed by ion implantation. Thus, the space ratio of a single pixel is reduced, the integration and device sensitivity are improved, and the blind pixel array and the pixel array are also in the same environment, thereby further improving the detection sensitivity and reducing the detection error.
-
公开(公告)号：US20220156570A1
公开(公告)日：2022-05-19
申请号：US17602804
申请日：2019-08-07
发明人： Ling SHEN , Yu JIANG , Huijie YAN , Zhifang LI , Jianxin WEN
IPC分类号： G06N3/063
摘要： A single-layered linear neural network based on a cell synapse structure comprising a pre-synapse and a post-synapse, the pre-synapse comprises a plurality of precursor resistors, number of the precursor resistors is m, one end of the precursor resistors in the pre-synapse is jointly connected with an intermediate point, and another end of the precursor resistors is respectively connected with each of a plurality of precursor signal input ends, number of the precursor signal input ends is m; the precursor signal input ends are used for receiving input voltages; the post-synapse comprises a plurality of posterior resistors, number of the precursor resistors is n, one end of the posterior resistors in the post-synapse is jointly connected with the intermediate point, and another end of the posterior resistors is respectively connected with each of a plurality of posterior signal output ends, number of the posterior signal output ends is n; the posterior signal output ends are used for outputting currents. The invention provides a single-layered linear neural network based on cell synapse structure, which can reduce the number of resistors; in addition, a weight between an external precursor neuron and an external posterior neuron can be changed only by adjusting two variable resistors or one of the two variable resistors.
-
公开(公告)号：US11264421B2
公开(公告)日：2022-03-01
申请号：US16643566
申请日：2018-08-29
发明人： Xingchen Ge
IPC分类号： H01L27/146
摘要： The present disclosure discloses a method for manufacturing a backside-illuminated CMOS image sensor structure, the method comprises: providing a silicon substrate which has been subjected to a frontside processing and a back thinning; forming grid-shaped deep trenchs on the back of the silicon substrate; forming an insulating layer on the inner wall surface of the deep trenchs to form a grid-shaped deep trenchs isolation structure; forming a diffusion barrier layer on the surface of the insulating layer; filling metal in the deep trenchs to form a grid-shaped composite structure in which the Metal grid is combined with the deep trenchs isolation structure.
-
公开(公告)号：US20220059402A1
公开(公告)日：2022-02-24
申请号：US17284849
申请日：2019-09-06
发明人： Weijun WANG , Hong LIN
IPC分类号： H01L21/762 , H01L21/308 , H01L21/3105 , H01L21/02 , H01L21/311 , H01L21/3065
摘要： The present invention discloses a formation method, comprising: forming a hard mask layer and a photo-lithographic pattern of a fin structure on a the semiconductor substrate; patterning the hard mask layer and the semiconductor substrate to gain the fin structure with a profile of steep sidewalls; forming a protective layer on the sidewall surface of the fin structure; etching the semiconductor substrate located below the fin structure to form isolation structure trenches; performing a modified treatment on the exposed surfaces of the isolation structure trenches to form a modified layer with a certain thickness; removing the protective layer and the modified layer simultaneously; filling a dielectric layer in the isolation structure trenches till to cover the fin structure and then planarizing the dielectric layer; performing a trench etching to the dielectric layer and forming the fin structure and an isolation structure with sloped sidewalls. The present invention adjusts physical profiles of the sidewalls of both the fin structure and the isolation structure independently, improves process accuracy, uniformity and stability, so as to improve electrical performance and device reliability of FET devices.
-
-
-
-
-
-
-
-
-
搜索结果
96 条记录 (耗时 0.024 秒)
