公开(公告)号：US20110271277A1

公开(公告)日：2011-11-03

申请号：US12769463

申请日：2010-04-28

Applicant: Muhammad Raghib Hussain ,  Rajan Goyal ,  Richard Kessler

Inventor： Muhammad Raghib Hussain ,  Rajan Goyal ,  Richard Kessler

IPC: G06F9/455 ,  G06F12/00 ,  G06F9/46

CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/0644 ,  G06F3/0664 ,  G06F3/0683 ,  G06F9/455 ,  G06F9/45558 ,  G06F9/5077 ,  G06F12/0653 ,  G06F12/084 ,  G06F12/0897 ,  G06F12/14 ,  G06F12/1458 ,  G06F2009/45583 ,  G06F2212/1008 ,  G06F2212/152 ,  G06F2212/62

Abstract: A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to each virtual system on chip.

Abstract translation: 虚拟片上系统（VSoC）是允许在不同虚拟系统之间共享底层物理机器资源的机器的实现。 本发明的方法或对应的装置涉及一种包括多个芯片上的虚拟系统和配置单元的设备。 配置单元被配置为根据分配给芯片上的每个虚拟系统的识别标签来配置芯片上的多个虚拟系统的设备上的资源。

公开(公告)号：US20110185203A1

公开(公告)日：2011-07-28

申请号：US12695648

申请日：2010-01-28

Applicant: David A. Carlson ,  Richard E. Kessler ,  Amer Haider

Inventor： David A. Carlson ,  Richard E. Kessler ,  Amer Haider

IPC: G06F1/00

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/329 ,  G06F11/3058 ,  Y02D10/24 ,  Y10S323/907

Abstract: Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power. Example embodiments may stall the issue or execution of instructions by the processor, allowing software or hardware to reduce the power of an application by imposing a decrease in the performance of the application.

Abstract translation: 本发明的实施例涉及限制在处理器中发生的最大功率耗散。 因此，当正在执行需要过多功率的应用时，可以防止应用的执行以减少耗散或消耗的功率。 示例性实施例可以阻止处理器发出或执行指令，允许软件或硬件通过施加应用的性能的降低而降低应用的功率。

公开(公告)号：US07941585B2

公开(公告)日：2011-05-10

申请号：US11015343

申请日：2004-12-17

Applicant: David H. Asher ,  David A. Carlson ,  Richard E. Kessler

Inventor： David H. Asher ,  David A. Carlson ,  Richard E. Kessler

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/084 ,  G06F9/30014 ,  G06F9/30138 ,  G06F9/383 ,  G06F11/3632 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0835 ,  G06F12/0875 ,  G06F12/0891 ,  G06F13/24 ,  G06F2212/6012 ,  G06F2212/6022

Abstract: A RISC-type processor includes a main register file and a data cache. The data cache can be partitioned to include a local memory, the size of which can be dynamically changed on a cache block basis while the processor is executing instructions that use the main register file. The local memory can emulate as an additional register file to the processor and can reside at a virtual address. The local memory can be further partitioned for prefetching data from a non-cacheable address to be stored/loaded into the main register file.

Abstract translation: RISC型处理器包括主寄存器文件和数据高速缓存。 可以将数据高速缓存分割成包括本地存储器，当处理器正在执行使用主寄存器文件的指令时，可以在缓存块的基础上动态地改变其大小。 本地存储器可以作为额外的寄存器文件模拟到处理器，并且可以驻留在虚拟地址处。 本地存储器可以被进一步分区以从不可缓存地址预取数据以被存储/加载到主寄存器文件中。

公开(公告)号：US20100050177A1

公开(公告)日：2010-02-25

申请号：US12229617

申请日：2008-08-25

Applicant: Rajan Goyal ,  Muhammad Raghib Hussain

Inventor： Rajan Goyal ,  Muhammad Raghib Hussain

IPC: G06F9/44

CPC classification number: G06F21/552

Abstract: The scheduling of multiple request to be processed by a number of deterministic finite automata-based graph thread engine (DTE) workstations is processed by a novel scheduler. The scheduler may select an entry from an instruction in a content search apparatus. Using attribute information from the selected entry, the scheduler may thereafter analyze a dynamic scheduling table to obtain placement information. The scheduler may determine an assignment of the entry, using the placement information, that may limit cache thrashing and head of line blocking occurrences. Each DTE workstation may including normalization capabilities. Additionally, the content searching apparatus may employ an address memory scheme that may prevent memory bottle neck issues.

Abstract translation: 由多个确定性有限自动机图形线程引擎（DTE）工作站处理的多个请求的调度由新的调度器处理。 调度器可以从内容搜索装置中的指令中选择一个条目。 使用来自所选条目的属性信息，调度器随后可以分析动态调度表以获得放置信息。 调度器可以使用放置信息来确定条目的分配，其可以限制高速缓存颠簸和线路阻塞发生的头部。 每个DTE工作站可以包括规范化功能。 此外，内容搜索装置可以采用可以防止存储瓶颈问题的地址存储器方案。

公开(公告)号：US20090138494A1

公开(公告)日：2009-05-28

申请号：US11986970

申请日：2007-11-27

Applicant: Rajan Goyal

Inventor： Rajan Goyal

IPC: G06F17/30

CPC classification number: G06F17/30985

Abstract: An apparatus, and corresponding method, for generating a graph used in performing a search for a match of at least one expression in an input stream is presented. The graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc of a current node represents a character match in an expression of a character associated with the current node. Arcs which are not valid may be pruned. Non-valid arcs may include arcs which point back to a designated node(s), or arcs that point to the same next node as the designated node(s) for the same character. Typically, the majority of arcs associated with a node are non-valid. Therefore, pruning the non-valid arcs may greatly reduce graph storage requirements.

Abstract translation: 提供了一种用于生成在执行搜索输入流中的至少一个表达式的匹配的图表的装置和相应方法。 该图包括由有效弧单独连接的多个互连节点。 当前节点的有效弧表示与当前节点相关联的字符的表达式中的字符匹配。 无效的弧可能会被修剪。 非有效弧可以包括指向指定节点的弧，或指向与相同字符的指定节点相同的下一个节点的弧。 通常，与节点相关联的大多数弧是无效的。 因此，修剪非有效的弧可能会大大降低图形存储要求。

公开(公告)号：US07337314B2

公开(公告)日：2008-02-26

申请号：US10411945

申请日：2003-04-12

Applicant: Muhammad Raghib Hussain ,  Philip H. Dickinson ,  Imran Badr

Inventor： Muhammad Raghib Hussain ,  Philip H. Dickinson ,  Imran Badr

IPC: H04L9/00 ,  H04L9/32 ,  G06F11/30 ,  G06F12/14

CPC classification number: H04L63/0428

Abstract: A security processing apparatus is described comprising: a cryptographic processor having a first plurality of security processing resources initially allocated to process a first type of data traffic and a second plurality of security processing resources initially allocated to process a second type of data traffic; a monitor module to monitor load on the first plurality of security processing resources and the second plurality of security processing resources as the first and second types of data traffic are processed; a resource allocation module to reallocate some of the first plurality of security processing resources from the first type of data traffic to the second type of data traffic if detected load on the second plurality of security processing resources is above a specified threshold value.

Abstract translation: 一种安全处理装置被描述为包括：密码处理器，其具有最初被分配以处理第一类型的数据业务的第一多个安全处理资源和最初被分配以处理第二类型的数据业务的第二多个安全处理资源; 处理第一和第二类型的数据业务的监视模块，用于监视第一多个安全处理资源上的负载和第二多个安全处理资源; 资源分配模块，用于在所述第二多个安全处理资源上检测到的负载时将所述第一多个安全处理资源中的一些从所述第一类型的数据业务重新分配到所述第二类型的数据业务，所述资源分配模块高于指定的阈值。

公开(公告)号：US07260217B1

公开(公告)日：2007-08-21

申请号：US10092328

申请日：2002-03-06

Applicant: David A. Carlson

Inventor： David A. Carlson

IPC: H04K1/04

CPC classification number: H04L9/065 ,  H04L2209/12 ,  H04L2209/34

Abstract: In one embodiment, a computer-implemented method comprises receiving a data cipher operation. The method also comprises processing the data cipher operation. The processing of the operation includes generating a number of portions of ciphertext from plaintext, wherein a load operation associated with the generating of at least one portion of the ciphertext executes prior to a store operation associated with the generating of a prior portion of the ciphertext.

Abstract translation: 在一个实施例中，计算机实现的方法包括接收数据密码操作。 该方法还包括处理数据密码操作。 操作的处理包括从明文生成密文的多个部分，其中与生成密文的至少一部分相关联的加载操作在与生成密文的先前部分相关联的存储操作之前执行。

公开(公告)号：US07240203B2

公开(公告)日：2007-07-03

申请号：US10025509

申请日：2001-12-19

Applicant: Richard E. Kessler ,  David A. Carlson ,  Muhammad Raghib Hussain ,  Robert A. Sanzone ,  Khaja E. Ahmed ,  Michael D. Varga

Inventor： Richard E. Kessler ,  David A. Carlson ,  Muhammad Raghib Hussain ,  Robert A. Sanzone ,  Khaja E. Ahmed ,  Michael D. Varga

IPC: H04L9/00

CPC classification number: H04L63/164 ,  G06F21/606

Abstract: A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a number of output data structures associated with the number of requests within a remote memory based on pointers stored in the number of requests. The number of execution units can output the results in an order that is different from the order of the requests in a request queue. The processor also includes a request unit coupled to the number of execution units. The request unit is to retrieve a portion of the number of requests from the request queue within the remote memory and associated input data structures for the portion of the number of requests from the remote memory. Additionally, the request unit is to distribute the retrieved requests to the number of execution units based on availability for processing by the number of execution units.

Abstract translation: 描述用于处理安全操作的方法和装置。 在一个实施例中，处理器包括多个执行单元，用于处理多个安全操作请求。 执行单元的数量是基于存储在请求数中的指针，将与多个与远程存储器内的请求数相关联的输出数据结构的请求数的结果输出。 执行单元的数量可以按照与请求队列中的请求顺序不同的顺序输出结果。 处理器还包括耦合到执行单元数量的请求单元。 请求单元从远程存储器中的请求队列中检索一部分请求数，并且从远程存储器中获取部分请求的相关联的输入数据结构。 此外，请求单元是基于执行单元的数量的处理的可用性将检索到的请求分发到执行单元的数量。

公开(公告)号：US07209531B1

公开(公告)日：2007-04-24

申请号：US10397083

申请日：2003-03-26

Applicant: Daniel A. Katz ,  Richard E. Kessler ,  Thucydides Xanthopoulos

Inventor： Daniel A. Katz ,  Richard E. Kessler ,  Thucydides Xanthopoulos

IPC: H04L7/00

CPC classification number: H04L7/0338 ,  H03K5/133 ,  H04L7/005 ,  H04L7/10

Abstract: A deskew circuit utilizing a coarse delay adjustment and fine delay adjustment centers the received data in a proper data window and aligns the data for proper sampling. In one scheme, bit state transitions of a training sequence for SPI-4 protocol is used to adjust delays to align the transition points.

Abstract translation: 利用粗略延迟调整和精细延迟调整的偏移电路将接收到的数据集中在适当的数据窗口中，并对准数据以进行适当的采样。 在一种方案中，SPI-4协议的训练序列的位状态转换用于调整延迟以对齐转换点。

公开(公告)号：US07961033B2

公开(公告)日：2011-06-14

申请号：US12586169

申请日：2009-09-17

Applicant: Scott Meninger ,  Kyoungho Woo

Inventor： Scott Meninger ,  Kyoungho Woo

IPC: G05F1/10

CPC classification number: H03L7/0812

Abstract: A temperature sensor includes an open-loop delay line comprising plural delay cells and a multiplexer configured to select a first number of the plural delay cells; a delay-locked loop comprising plural delay cells and a multiplexer configured to select a second number of the plural delay cells; a clock coupled to an input of the open-loop delay line and to an input of the delay-locked loop; a detector having a first input coupled to an output of the open-loop delay line and a second input coupled to an output of the delay-locked loop; and a finite state machine configured to detect a transition in the output of the phase detector.

Abstract translation: 温度传感器包括：开环延迟线，包括多个延迟单元;多路复用器，被配置为选择多个延迟单元的第一数量; 延迟锁定环路，包括多个延迟单元和被配置为选择所述多个延迟单元的第二数量的多路复用器; 耦合到开环延迟线的输入和延迟锁定环的输入的时钟; 检测器，其具有耦合到所述开环延迟线的输出的第一输入和耦合到所述延迟锁定环的输出的第二输入; 以及被配置为检测相位检测器的输出中的转变的有限状态机。