公开(公告)号：US20190197763A1

公开(公告)日：2019-06-27

申请号：US16232799

申请日：2018-12-26

申请人： Dassault Systemes

发明人： Gilles Laurent ,  Cyril Delalandre ,  Tamy Boubekeur

IPC分类号： G06T15/20 ,  G06F7/57 ,  G06F17/16 ,  G06T1/20 ,  G06T1/60

CPC分类号： G06T15/20 ,  G06F7/57 ,  G06F17/16 ,  G06T1/20 ,  G06T1/60 ,  G06T15/08 ,  G06T15/40 ,  G06T2210/21

摘要： The disclosure notably relates to a computer-implemented method of computing a visibility function of a 3D scene. The method includes obtaining a set of directions ({right arrow over (ω)}) in the 3D scene, computing a set of lines that are parallel to the direction, for each computed set of lines, sampling the lines of the set into spatial segments, associating each line of a set with a bit field, each spatial segment of the line corresponding to a bit of the bit field, superimposing the set of lines and the 3D scene, when a spatial segment of a line intersects a geometry in the 3D scene, marking the bit, corresponding to the spatial segment of the bit field, associated with the line, obtaining two points in the 3D scene, identifying spatial segments having a closest alignment with the query segment, computing the visibility of the query segment by performing a logical bit operation.

公开(公告)号：US10313495B1

公开(公告)日：2019-06-04

申请号：US15682365

申请日：2017-08-21

申请人： Barefoot Networks, Inc.

发明人： Patrick Bosshart ,  Michael Gregory Ferrara ,  Michael E. Attig ,  Jay Evan Scott Peterson

IPC分类号： H04L12/50 ,  H04L29/06 ,  H04L12/721 ,  H04L12/741 ,  G06F9/30 ,  H04L12/24 ,  G06F7/57

摘要： A method of configuring a forwarding element that includes several data plane message processing stages. The method stores a set of action codes in an instruction memory in the data plane of the forwarding element. Each action code identifies an operation to perform on a field of a message received at the data plane. The method determines action codes required to process each field of the message in each message processing stage. The method configures a data-plane processing unit of the forwarding element to concurrently perform a group of the action codes in the same data plane processing stage when (i) the action codes are the same and (ii) operate on the same field of the message.

公开(公告)号：US20190163475A1

公开(公告)日：2019-05-30

申请号：US15822515

申请日：2017-11-27

申请人： Advanced Micro Devices, Inc.

发明人： John M. King

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F12/0875 ,  G06F7/57

摘要： Described herein is a system and method for store fusion that fuses small store operations into fewer, larger store operations. The system detects that a pair of adjacent operations are consecutive store operations, where the adjacent micro-operations refers to micro-operations flowing through adjacent dispatch slots and the consecutive store micro-operations refers to both of the adjacent micro-operations being store micro-operations. The consecutive store operations are then reviewed to determine if the data sizes are the same and if the store operation addresses are consecutive. The two store operations are then fused together to form one store operation with twice the data size and one store data HI operation.

公开(公告)号：US10275220B2

公开(公告)日：2019-04-30

申请号：US15688039

申请日：2017-08-28

申请人： FUJITSU LIMITED

发明人： Sota Sakashita

IPC分类号： G06F7/57 ,  G06F9/48 ,  G06F9/38 ,  G06F9/30 ,  G06F9/50 ,  H04W88/02

摘要： An arithmetic processing device includes: a decode circuit configured to decode instructions; an execution control circuit configured to hold the instructions decoded by the decode circuit and to output the held instructions in an executable order; an instruction transfer circuit configured to sequentially transfer the instructions sequentially output by the execution control circuit; an instruction generation circuit configured to output, to the instruction transfer circuit, an individual instruction generated from a combined instruction in a case where one of the instructions transferred by the instruction transfer circuit is the combined instruction obtained by combining individual instructions; and an arithmetic execution circuit configured to execute the individual instruction transferred by the instruction transfer circuit.

公开(公告)号：US20190122100A1

公开(公告)日：2019-04-25

申请号：US16160444

申请日：2018-10-15

申请人： Samsung Electronics Co., Ltd.

发明人： Shinhaeng KANG ,  Seungwon LEE

IPC分类号： G06N3/063 ,  G06N3/08 ,  G06F7/499 ,  G06F7/57

摘要： Provided is a processor implemented method that includes performing training or an inference operation with a neural network by obtaining a parameter for the neural network in a floating-point format, applying a fractional length of a fixed-point format to the parameter in the floating-point format, performing an operation with an integer arithmetic logic unit (ALU) to determine whether to round off a fixed point based on a most significant bit among bit values to be discarded after a quantization process, and performing an operation of quantizing the parameter in the floating-point format to a parameter in the fixed-point format, based on a result of the operation with the ALU.

公开(公告)号：US20190004795A1

公开(公告)日：2019-01-03

申请号：US16015789

申请日：2018-06-22

申请人： FUJITSU LIMITED

发明人： Masahiro Kuramoto

IPC分类号： G06F9/30 ,  G06F7/57

摘要： An arithmetic processing device includes, a memory that stores a first data and a second data, a plurality of arithmetic circuits, a first memory arranged for each of the arithmetic circuits and that stores a first predetermined row having the predetermined number of the first data stored in the memory, a second memory arranged for each of the arithmetic circuits and that stores a second predetermined row having a predetermined number of the second data stored in the memory, and a plurality of multiply-add arithmetic circuits arranged for each of the arithmetic circuits, a number of the multiply-add arithmetic circuits corresponding to the predetermined number, each of the multiply-add arithmetic circuits that obtains a third data by executing the operation using the first data and the second data based on a result of performing a row operation which is an operation of one row of the first data.

公开(公告)号：US20180204389A1

公开(公告)日：2018-07-19

申请号：US15873326

申请日：2018-01-17

申请人： CASIO COMPUTER CO., LTD.

发明人： Hirokazu TANAKA

IPC分类号： G06T19/20 ,  G06F17/17 ,  G06T15/10 ,  G06F7/57

摘要： According one embodiment, there is provided a drawing method, that comprises: when at least part of a first surface and at least part of a second surface are practically congruent to each other in a three-dimensional coordinate system, assigning each of a first drawing pattern related to the first surface and a second drawing pattern related to the second surface to any one of more than one unit drawing area forming the at least part of the first surface or the at least part of the second surface, drawing the more than one unit drawing area by using the first drawing pattern and the second drawing pattern each assigned to any one of the more than one unit drawing area, and thereby drawing the at least part of the first surface or the second surface.

公开(公告)号：US20170288684A1

公开(公告)日：2017-10-05

申请号：US15624931

申请日：2017-06-16

申请人： OLYMPUS CORPORATION

发明人： Tomoharu OGIHARA

IPC分类号： H03L7/095 ,  G06F7/57 ,  H03K19/177

CPC分类号： H03L7/095 ,  G06F7/57 ,  H03K19/17716

摘要： A processing apparatus includes an FPGA unit connected to an oscillator configured to output a first clock, wherein the FPGA unit includes: a PLL circuit configured to output a second clock with a frequency of a predetermined ratio with respect to a frequency of the first clock and configured to output a lock signal (detection signal); an input and output monitoring unit configured to detect a ratio between the frequencies of the first clock and the second clock, compare the detected ratio with the predetermined ratio, and output an abnormal signal when the detected ratio does not coincide with the predetermined ratio; and an initialization unit configured to output a reset signal when the input and output monitoring unit outputs the abnormal signal and configured to output the reset signal when the PLL circuit outputs the lock signal.

公开(公告)号：US20170212968A1

公开(公告)日：2017-07-27

申请号：US15405328

申请日：2017-01-13

申请人： Easy-Logic Technology Limited

发明人： Yi DIAO ,  Xing WEI ,  Yu-Liang WU

IPC分类号： G06F17/50 ,  G06F7/57

CPC分类号： G06F17/504 ,  G06F17/5022

摘要： A method enables arithmetic circuit verification with improved runtime complexity by coupling reverse engineering and a SAT solver together. The method provides a netlist f of a first arithmetic circuit and a netlist g of a second arithmetic circuit; and improves the runtime complexity by conducting equivalence checking between the netlist f and the netlist g such that structural difference between the netlist f and the netlist g is minimized by reverse engineering before generating a conjunctive normal form (CNF) encoding that is solved by a satisfiability (SAT) solver such that the arithmetic circuit verification is completed in polynomial time rather than in exponential time.

公开(公告)号：US09698779B2

公开(公告)日：2017-07-04

申请号：US14506216

申请日：2014-10-03

申请人： Texas Instruments Incorporated

发明人： Devanathan Varadarajan ,  Karthik Srinivasan ,  Neel Talakshi Gala

IPC分类号： G06F7/57 ,  H03K19/00 ,  H03K19/177

CPC分类号： H03K19/0008 ,  H03K19/17752 ,  H03K19/17764

摘要： Methods for reconfiguring an ASIC at runtime without using voltage over scaling. A functional criticality of a set of logic in the ASIC is identified. Then, the set of logic are classified into a set of regions based on the functional criticality, each region of the set of regions having a target error threshold. Further, each region is power gated at runtime based on the functional criticality such that the target error threshold is achieved without using voltage over scaling.