公开(公告)号：US20070011595A1

公开(公告)日：2007-01-11

申请号：US11493273

申请日：2006-07-26

申请人： Kelly Cameron ,  Ba-Zhong Shen ,  Hau Tran

发明人： Kelly Cameron ,  Ba-Zhong Shen ,  Hau Tran

IPC分类号： H03M13/03

CPC分类号： H03M13/3905 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2957 ,  H03M13/3988 ,  H03M13/6362 ,  H03M13/6516

摘要： Communication decoder employing single trellis to support multiple code rates and/or multiple modulations. A single trellis is employed by the decoder to decode a plurality of encoded symbols. Each of the plurality of encoded symbols is governed by a rate control. A rate control sequence, having a period, is used to decode the plurality of encoded symbols that may be arranged within a frame. Various parameters of the plurality of encoded symbols may vary on a symbol by symbol basis; these parameters may include modulation, constellation, mapping, and/or bandwidth efficiency. For example, various symbols may be encoded differently, yet they may all be decoded using the same trellis. The functionality of this decoder may be implemented within a variety of different decoder embodiments including a trellis code modulation (TCM) decoder, a turbo trellis code modulation (TTCM) decoder, and/or a parallel concatenated turbo code modulation (PC-TCM) decoder.

摘要翻译： 采用单网格的通信解码器支持多种码率和/或多种调制方式。 解码器使用单个网格来解码多个编码符号。 多个编码符号中的每一个由速率控制来控制。 具有周期的速率控制序列用于解码可以布置在帧内的多个编码符号。 多个编码符号的各种参数可以逐个符号地变化; 这些参数可以包括调制，星座图，映射和/或带宽效率。 例如，各种符号可以被不同地编码，但是它们都可以使用相同的网格进行解码。 该解码器的功能可以在各种不同的解码器实施例中实现，包括网格码调制（TCM）解码器，turbo网格码调制（TTCM）解码器和/或并行级联的turbo码调制（PC-TCM）解码器 。

公开(公告)号：US07012975B2

公开(公告)日：2006-03-14

申请号：US09952309

申请日：2001-09-12

申请人： Hau Thien Tran ,  Kelly B. Cameron ,  Ba-Zhong Shen ,  Christopher R. Jones

发明人： Hau Thien Tran ,  Kelly B. Cameron ,  Ba-Zhong Shen ,  Christopher R. Jones

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Method and apparatus for performing calculations for forward (alpha) and reverse (beta) metrics in a map decoder. The method includes using a min star (min*) operation to receive the metrics and a priori values as well as forming min star structures from individual min star operations. Two separate outputs from the min star operation may be maintained separately throughout all calculations and combined only when a final value is required. In addition input to the min star operators that are available prior to a particular decoder iteration may be combined separately to allow an increase in speed within decoding iterations. The same principals apply to the more popular max star operation.

公开(公告)号：US20050022090A1

公开(公告)日：2005-01-27

申请号：US10897201

申请日：2004-07-22

申请人： Kelly Cameron ,  Hau Tran ,  Ba-Zhong Shen ,  Christopher Jones

发明人： Kelly Cameron ,  Hau Tran ,  Ba-Zhong Shen ,  Christopher Jones

IPC分类号： H03M13/15 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H03M13/41 ,  H03M13/45 ,  H04L1/00 ,  G06F7/00 ,  G06F17/30 ,  H03M13/00 ,  H04L5/12 ,  H04L23/02

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

公开(公告)号：US06816556B2

公开(公告)日：2004-11-09

申请号：US09758168

申请日：2001-01-12

申请人： Jin-sook Kim

发明人： Jin-sook Kim

IPC分类号： H04L2302

CPC分类号： H04L1/005 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2957 ,  H03M13/3988 ,  H03M13/4146 ,  H03M13/6362 ,  H03M13/6577 ,  H04L1/0041 ,  H04L1/006 ,  H04L1/0066

摘要： A bandwidth-efficient concatenated trellis-coded modulation (TCM) decoder which is realized by combining turbo codes having an advantage of coping effectively with a fading channel with TCM having an advantage of bandwidth efficiency, and a decoding method thereof are provided. A conventional TCM method has high bandwidth efficiency suitable for transmitting information at high speed. However, it is very sensitive to InterSymbol interference (ISI) so it is usually applied to a wire communication system rather than to a wireless communication system. A turbo code method is an error correction encoding method showing steadiness in a channel having severe ISI and having an excellent error correction ability, but has drawbacks of low data transmission rate and low bandwidth efficiency due to a low code rate. Bandwidth-efficient concatenated TCM is provided for enhancing the steadiness against ISI and-improving power and bandwidth efficiency by applying the turbo code method to a TCM having a code rate of m/(m+1) to compensate for the drawbacks of the conventional TCM and turbo codes. A newly provided decoding method in bandwidth-efficient concatenated TCM uses a SOVA algorithm, thereby reducing decoder complexity and path memory. In addition, bandwidth-efficient concatenated TCM encoder and decoder are provided such to have parallel transition, thereby reducing the complexity of the bandwidth-efficient concatenated TCM decoder. Therefore, the Bandwidth-efficient concatenated TCM is applied to a high speed wireless communication system and can increase bandwidth efficiency and coding gain.

摘要翻译： 提供了一种带宽有效的级联网格编码调制（TCM）解码器，其通过组合具有有效地与具有带宽效率的优点的TCM的衰落信道有效地应用的turbo码来实现，及其解码方法。 传统的TCM方法具有高带宽效率，适用于高速传输信息。 然而，它对InterSymbol干扰（ISI）非常敏感，因此它通常应用于有线通信系统而不是无线通信系统。 涡轮编码方法是一种误差校正编码方法，其显示具有严重ISI并且具有优异的纠错能力的信道的稳定性，但由于码率低而具有低数据传输速率和低带宽效率的缺点。 提供带宽有效的级联TCM，用于通过将turbo码方法应用于码率为m /（m + 1）的TCM来补偿传统TCM的缺点，增强了对ISI的稳定性和提高功率和带宽效率 和turbo码。 带宽效率级联TCM中新提供的解码方法采用SOVA算法，从而降低了解码器的复杂度和路径记忆。 另外，带宽有效的级联TCM编码器和解码器被提供为具有并行转换，从而降低带宽有效级联TCM解码器的复杂性。 因此，将带宽有效的级联TCM应用于高速无线通信系统，并可以提高带宽效率和编码增益。

公开(公告)号：US20030088821A1

公开(公告)日：2003-05-08

申请号：US10111744

申请日：2002-09-19

发明人： Takashi Yokokawa ,  Toshiyuki Miyauchi ,  Kouhei Yamamoto

IPC分类号： G06F011/00 ,  H03M013/03

CPC分类号： H03M13/2767 ,  H03M13/235 ,  H03M13/2771 ,  H03M13/2903 ,  H03M13/2987 ,  H03M13/3911 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/41 ,  H03M13/6516 ,  H03M13/6566 ,  H03M13/6572 ,  H04L1/0043 ,  H04L1/0052 ,  H04L1/0055 ,  H04L1/0059 ,  H04L1/0066 ,  H04L1/0071

摘要： To implement plural types of interleaving for decoding each of various codes in an adaptively suitable manner for the code by a simple circuit construction, an interleaver (100) in an element decoder includes a plurality of data storage circuits (407), and in addition, a control circuit (400) which generates address data for use to write data to the storage circuits (407) and address data for use to read date from the storage circuits (400), an address data selection circuit (405) which selects address data to be distributed to the plurality of storage circuits (407) according to a mode indicating the configuration of a code including the type of an interleaving to be done, an input data selection circuit (406) which selects data to be distributed to the plurality of storage circuits (407) according to the mode, and an output data selection circuit (408) which selects data to be outputted according to the mode. Of the plural storage circuits (407), a one to be used is selected.

摘要翻译： 为了通过简单的电路结构以自适应的方式实现用于对各种代码进行解码的多种类型的交织，元件解码器中的交织器（100）包括多个数据存储电路（407），另外， 生成用于向存储电路（407）写入数据的地址数据和用于从存储电路（400）读取日期的地址数据的控制电路（400），选择地址数据的地址数据选择电路（405） 根据指示包括要完成的交织类型的代码的配置的模式分配给多个存储电路（407）;输入数据选择电路（406），其选择要分配给多个 根据该模式的存储电路（407）以及根据该模式选择要输出的数据的输出数据选择电路（408）。 在多个存储电路（407）中，选择要使用的存储电路。

公开(公告)号：US20020126776A1

公开(公告)日：2002-09-12

申请号：US10023543

申请日：2001-12-17

发明人： Markus Muck ,  Ralf Hekmann

IPC分类号： H04L027/06

CPC分类号： H03M13/6325 ,  H03M13/3961 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6502 ,  H04L1/0054

摘要： A Viterbi decoder including an Add-Select-Compare unit with a new butterfly unit (300) having only two adders (310, 320), compared with a conventional butterfly unit's four adders, for processing a trellis transition having branch metric of zero. The new butterfly unit (300) is thus of reduced complexity (saving 8% of the total Viterbi decoder complexity in a typical example). Methods are also disclosed for producing suitable metrics for use with the new butterfly unit, and for optimizing these metrics by dynamic scaling (particularly suitable for OFDM applications) and adaptation for additive noise. The invention is particularly suitable for high speed, low-power implementations for broadband communications applications, and may be implemented in software or hardware.

摘要翻译： 一种维特比解码器，其与具有仅具有两个加法器（310,320）的新蝶形单元（300）相比，具有用于处理具有分支度量为零的网格转换的常规蝶形单元的四个加法器的添加选择比较单元。 因此，新的蝶形单元（300）的复杂度降低（在典型的示例中，节省了维特比解码器总复杂度的8％）。 还公开了用于产生用于新蝴蝶单元的合适度量的方法，并且通过动态缩放（特别适合于OFDM应用）和适应加性噪声优化这些度量。 本发明特别适合用于宽带通信应用的高速，低功率实现，并且可以以软件或硬件来实现。

公开(公告)号：US20020061078A1

公开(公告)日：2002-05-23

申请号：US09952312

申请日：2001-09-12

发明人： Kelly B. Cameron

IPC分类号： H04L027/06

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Method and apparatus for Soft In Soft Out Turbo Code Decoder. Metrics are received by a decoder having SISO unit(s). The SISO unit computes all the alpha values corresponding to a block of data. Of the alpha values computed some alpha values, for example alpha values selected at regular intervals, corresponding to checkpoint values are pushed on a checkpoint stack. Alpha values are computed with some being saved as checkpoint values and some being discarded are computed until the computation reaches a predetermined distance from the end of the block of data. Once the predetermined distance is reached all alpha values are pushed on a computation stack. Once all the values corresponding to the values between the predetermined end of the block and the end of the block have been computed and placed in the computation stack they may be combined with beta values to produce extrinsic values. Once all the values have been used from the computation stack the next checkpoint value can be used to compute another computation stack of alpha values. The alpha values can then be combined with beta values to form extrinsic values and the process continued.

摘要翻译： 软输出Turbo码解码器的方法和装置。 度量由具有SISO单元的解码器接收。 SISO单元计算对应于数据块的所有α值。 计算一些alpha值的Alpha值，例如以定期间隔选择的对应于检查点值的alpha值被推送到检查点堆栈。 计算Alpha值，其中一些被保存为检查点值，并且计算一些被丢弃的值，直到计算达到距数据块结束的预定距离。 一旦达到预定距离，所有的阿尔法值被推送到计算堆栈上。 一旦对应于块的预定端和块结束之间的值的所有值已经被计算并被放置在计算堆栈中，它们可以与β值组合以产生外在值。 一旦从计算堆栈中使用了所有的值，可以使用下一个检查点值来计算alpha值的另一个计算堆栈。 然后可以将α值与β值组合以形成外在值，并且该过程继续。

公开(公告)号：US20020025005A1

公开(公告)日：2002-02-28

申请号：US09919191

申请日：2001-07-31

发明人： Eko N. Onggosanusi ,  Alan Gatherer

IPC分类号： H04L027/04 ,  H04L027/12 ,  H04L027/20

CPC分类号： H04L1/006 ,  H03M13/258 ,  H03M13/3988 ,  H04L1/0041 ,  H04L1/0066

摘要： Parallel concatenated trellis-coding modulation is accomplished by producing coded bits (21) from uncoded bits and also producing an interleaved version (22) of the coded bits from the uncoded bits. A first coded bits-to-signal mapping (mapping 1) is applied to the coded bits to produce a first output signal (S11), and a second coded bits-to-signal mapping (mapping 2) is applied to the interleaved version of the coded bits to produce a second output signal (S22), wherein the second coded bits-to-signal mapping differs from the first coded bits-to-signal mapping.

摘要翻译： 通过从未编码比特产生编码比特（21）并且还从未编码比特产生编码比特的交织版本（22）来实现并行级联网格编码调制。 将第一编码比特到信号映射（映射1）应用于编码比特以产生第一输出信号（S11），并且将第二编码比特到信号映射（映射2）应用于交织版本 所述编码比特产生第二输出信号（S22），其中所述第二编码比特到信号映射与所述第一编码比特到信号映射不同。

公开(公告)号：US06334202B1

公开(公告)日：2001-12-25

申请号：US09120203

申请日：1998-07-22

申请人： Stefan Pielmeier

发明人： Stefan Pielmeier

IPC分类号： H03M1303

CPC分类号： H03M13/6505 ,  H03M13/3961 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6569

摘要： A method and apparatus are used for determining a metric in a decoding algorithm, such as a Viterbi algorithm, using an n-bit processing module, on the basis of plural m-bit soft input words, wherein n≧2×m. The technique comprises: receiving plural m-bit soft input words; assembling at least two of the plural m-bit soft input words into a single n-bit composite soft input word; computing the respective distances between the at least two soft input words in the composite soft input word and expected codeword values to produce a composite distance word; summing the respective distances together to produce the metric; and extracting the metric. The n-bit processing module may comprise a 16-bit processing module employing 16-bit words, and the m-bit soft input words may each comprise a 4-bit word. Processing the plural soft input words en bloc increases the speed and information transfer rate of the decoder, and reduces the memory requirements of the decoder.

摘要翻译： 使用方法和装置，在多个m位软输入字的基础上，使用n比特处理模块来确定诸如维特比算法的解码算法中的度量，其中n> = 2xm。 该技术包括：接收多个m位软输入字; 将多个m位软输入字中的至少两个组合成单个n位复合软输入字; 计算复合软输入字中的至少两个软输入字与预期码字值之间的相应距离，以产生复合距离字; 将各个距离相加在一起以产生度量; 并提取度量。 n位处理模块可以包括采用16位字的16位处理模块，并且m位软输入字可以各自包括4位字。 整合处理多个软输入字增加了解码器的速度和信息传输速率，并且降低了解码器的存储器要求。

公开(公告)号：US20010047502A1

公开(公告)日：2001-11-29

申请号：US09821008

申请日：2001-03-29

发明人： Masayuki Hattori ,  Jun Murayama ,  Toshiyuki Miyauchi ,  Kouhei Yamamoto ,  Takashi Yokokawa

IPC分类号： G06F011/00 ,  H03M013/00 ,  H03M013/03

CPC分类号： H03M13/256 ,  H03M13/258 ,  H03M13/2972 ,  H03M13/3988

摘要： To carry out error correction coding and decoding according to a serially concatenated coded modulation system with a small circuit scale and high performance. A coding apparatus 1 is designed so that an interleaver 20 interleaves order of bits so that all weights are coded by a convolutional coder 30 with respect to data comprising a series of 3 bits supplied from a convolutional coder 10; the convolutional coder 30 makes as small as possible the total value of the hamming distance of input bit between passes to be the minimum Euclidean distance with respect to data of 3 bits supplied from the interleaver 20; and a multi-value modulation mapping circuit 40 causes the hamming distance of input bits in the convolutional coder 30 as the distance between signal point on the I/Q plane is smaller to subject data of 3 bits supplied from the convolutional coder 30 to mapping.

摘要翻译： 根据串行级联的编码调制系统，具有小电路规模和高性能，进行纠错编码和解码。 编码装置1被设计成使得交织器20交织比特的顺序，使得所有权重相对于包括从卷积编码器10提供的一系列3比特的数据由卷积编码器30编码; 卷积编码器30相对于从交织器20提供的3比特的数据，尽可能地使输入比特的汉明距离的总值为最小欧几里得距离; 并且多值调制映射电路40使卷积编码器30中的输入比特的汉明距离随着I / Q平面上的信号点之间的距离变小，从卷积编码器30提供的3比特数据映射。