公开(公告)号：US20140285237A1

公开(公告)日：2014-09-25

申请号：US14296283

申请日：2014-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Greg King

IPC: H03K19/0948 ,  H03K19/003 ,  H03K19/094

CPC classification number: H03K19/0948 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1096 ,  H03K19/00315 ,  H03K19/09429

Abstract: Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node.

Abstract translation: 存储器，驱动器电路和用于响应于输入信号产生输出信号的方法。 一个这样的驱动器电路包括输入级和输出级。 输入级接收输入信号并提供相对于输入信号具有延迟的延迟输入信号。 输出级接收延迟的输入信号，并进一步接收输入信号的补码。 响应于具有第一逻辑电平的输入信号的补码，输出级将输出节点耦合到第一电压，并且响应于具有第二逻辑电平的输入信号的补码将输出耦合到第二电压。 响应于接收延迟的输入信号，输出级进一步使输出与第一或第二电压分离，以在输出节点处提供高阻抗。

公开(公告)号：US20130285755A1

公开(公告)日：2013-10-31

申请号：US13911876

申请日：2013-06-06

Applicant: Fujitsu Semiconductor Limited

Inventor： Kristopher Kevin Kaufman ,  John Wayne Simmons

IPC: H03K3/36

CPC classification number: H03K3/36 ,  H03B5/02 ,  H03B5/1206 ,  H03B5/1228 ,  H03B5/364 ,  H03B2200/0012 ,  H03B2200/0026 ,  H03B2200/0046 ,  H03F3/72 ,  H03K19/09429

Abstract: In accordance with some embodiments of the present disclosure, an oscillator circuit comprises, a first pad associated with a first terminal of an oscillator and a second pad associated with a second terminal of the oscillator. The oscillator is configured to generate an oscillating signal and communicate the oscillating signal from the second terminal to a clock distributor coupled to the second pad. The oscillator circuit further comprises an oscillator gain element comprising an output node coupled to the first pad and an input node coupled to the second pad. The oscillator circuit also comprises a digital-to-analog converter (DAC) coupled to the first pad. The oscillator circuit additionally comprises a switching circuit coupled to the gain element. The switching circuit is configured to enable the gain element when the oscillator comprises a resonator and disable the gain element when the oscillator comprises a voltage controlled oscillating module.

Abstract translation: 根据本公开的一些实施例，振荡器电路包括：与振荡器的第一端子相关联的第一焊盘和与振荡器的第二端子相关联的第二焊盘。 振荡器被配置为产生振荡信号并将振荡信号从第二终端传送到耦合到第二焊盘的时钟分配器。 振荡器电路还包括振荡器增益元件，其包括耦合到第一焊盘的输出节点和耦合到第二焊盘的输入节点。 振荡器电路还包括耦合到第一焊盘的数模转换器（DAC）。 振荡器电路还包括耦合到增益元件的开关电路。 开关电路被配置为当振荡器包括谐振器时启用增益元件，并且当振荡器包括电压控制的振荡模块时禁用增益元件。

公开(公告)号：US20120280842A1

公开(公告)日：2012-11-08

申请号：US13100656

申请日：2011-05-04

Applicant: Kristopher Kevin Kaufman ,  John Wayne Simmons

Inventor： Kristopher Kevin Kaufman ,  John Wayne Simmons

IPC: H03M1/00 ,  H03L7/00

CPC classification number: H03K3/36 ,  H03B5/02 ,  H03B5/1206 ,  H03B5/1228 ,  H03B5/364 ,  H03B2200/0012 ,  H03B2200/0026 ,  H03B2200/0046 ,  H03F3/72 ,  H03K19/09429

Abstract: In accordance with some embodiments of the present disclosure, an oscillator circuit comprises, a first pad associated with a first terminal of an oscillator and a second pad associated with a second terminal of the oscillator. The oscillator is configured to generate an oscillating signal and communicate the oscillating signal from the second terminal to a clock distributor coupled to the second pad. The oscillator circuit further comprises an oscillator gain element comprising an output node coupled to the first pad and an input node coupled to the second pad. The oscillator circuit also comprises a digital-to-analog converter (DAC) coupled to the first pad. The oscillator circuit additionally comprises a switching circuit coupled to the gain element. The switching circuit is configured to enable the gain element when the oscillator comprises a resonator and disable the gain element when the oscillator comprises a voltage controlled oscillating module.

Abstract translation: 根据本公开的一些实施例，振荡器电路包括：与振荡器的第一端子相关联的第一焊盘和与振荡器的第二端子相关联的第二焊盘。 振荡器被配置为产生振荡信号并将振荡信号从第二终端传送到耦合到第二焊盘的时钟分配器。 振荡器电路还包括振荡器增益元件，其包括耦合到第一焊盘的输出节点和耦合到第二焊盘的输入节点。 振荡器电路还包括耦合到第一焊盘的数模转换器（DAC）。 振荡器电路还包括耦合到增益元件的开关电路。 开关电路被配置为当振荡器包括谐振器时启用增益元件，并且当振荡器包括电压控制的振荡模块时禁用增益元件。

公开(公告)号：US07710153B1

公开(公告)日：2010-05-04

申请号：US11479618

申请日：2006-06-30

Applicant: Robert P. Masleid ,  Scott Pitkethly

Inventor： Robert P. Masleid ,  Scott Pitkethly

IPC: H03K19/094

CPC classification number: H03K19/09429 ,  H03K17/002

Abstract: A cross point switch, in accordance with one embodiment of the present invention, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.

Abstract translation: 根据本发明的一个实施例的交叉点开关包括耦合以形成多个多路复用器的多个三态中继器。 多个多路复用器中的每组相应的三态中继器共享前端模块，使得与传统的交叉点开关相比，由于输入电容而导致的交叉点开关的延迟减小。

公开(公告)号：US07602219B2

公开(公告)日：2009-10-13

申请号：US12034298

申请日：2008-02-20

Applicant: Raimondo Luzzi ,  Marco Bucci

Inventor： Raimondo Luzzi ,  Marco Bucci

IPC: G06F7/58 ,  H03B5/24 ,  H03B29/00 ,  H03H11/16 ,  H03K3/03 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/0948

CPC classification number: H03K19/09429 ,  G06F7/588 ,  H03K3/0315 ,  H03K3/84 ,  H04L9/0863

Abstract: An inverting cell including a first inverter having first and second inputs; a second inverter having first and second inputs, wherein the second input of the second inverter is connected to the first input of the first inverter and the output of the first and second inverters is connected to the second input of the first inverter; and a third inverter connected between the output of the first and second inverters and the first input of the second inverter.

Abstract translation: 一种反相单元，包括具有第一和第二输入的第一反相器; 具有第一和第二输入的第二反相器，其中第二反相器的第二输入端连接到第一反相器的第一输入端，第一和第二反相器的输出端连接到第一反相器的第二输入端; 以及连接在第一和第二逆变器的输出端与第二反相器的第一输入端之间的第三反相器。

公开(公告)号：US07567094B2

公开(公告)日：2009-07-28

申请号：US11807150

申请日：2007-05-25

Applicant: Kalpendu Shastri

Inventor： Kalpendu Shastri

IPC: H03K19/00 ,  H03K19/02

CPC classification number: H03K19/09429

Abstract: A CMOS driver circuit is configured to provide a tri-state condition after a predetermined number of like-valued data bits have been transmitted, reducing the presence of intersymbol interference (ISI) along a transmission channel. In situations where the transmission channel is bandwidth-limited, the use of the tri-stating technique allows for the complete transition to the supply rails during the given bit period.

Abstract translation: CMOS驱动器电路被配置为在已经发送了预定数量的类似值的数据位之后提供三态条件，从而减少了沿着传输信道的符号间干扰（ISI）的存在。 在传输信道受带宽限制的情况下，三态技术的使用允许在给定位周期期间完全转换到电源轨。

公开(公告)号：US20090184737A1

公开(公告)日：2009-07-23

申请号：US12138024

申请日：2008-06-12

Applicant: Mi Hye Kim ,  Jae Jin Lee

Inventor： Mi Hye Kim ,  Jae Jin Lee

IPC: H03B1/00

CPC classification number: H03K19/00323 ,  G11C7/1078 ,  G11C7/1084 ,  H03K19/01721 ,  H03K19/01742 ,  H03K19/018528 ,  H03K19/09429

Abstract: A semiconductor device stabilizes an operation of an input buffer. A semiconductor device includes an input potential detection unit outputting a detection signal in response to a level of an input signal. An input buffer buffers the input signal by performing a differential amplifying operation through a first current sink unit. A second current sink unit, sharing an output with the input buffer, differentially amplifies the input signal of the input buffer in response to a level of the detection signal.

Abstract translation: 半导体器件稳定输入缓冲器的操作。 半导体器件包括输入电位检测单元，其响应于输入信号的电平输出检测信号。 输入缓冲器通过执行通过第一电流吸收器单元的差分放大操作来缓冲输入信号。 与输入缓冲器共享输出的第二电流宿单元响应于检测信号的电平差分地放大输入缓冲器的输入信号。

公开(公告)号：US20090066372A1

公开(公告)日：2009-03-12

申请号：US12204084

申请日：2008-09-04

Applicant: Michele LA PLACA ,  Ignazio Martines

Inventor： Michele LA PLACA ,  Ignazio Martines

IPC: H03K3/00 ,  H01R43/00

CPC classification number: H03K19/0013 ,  G11C7/1051 ,  G11C7/1057 ,  H03K19/01721 ,  H03K19/018571 ,  H03K19/09429 ,  Y10T29/49117

Abstract: An output CMOS buffer includes MOS enhancement transistors and has a second complementary pair of natural or low threshold transistors, connected respectively in parallel to transistors of opposite type of conductivity of the complementary pair of enhancement MOS transistors of the final buffer stage. The gate terminals of the pair of natural or low threshold transistors are controlled by respective inverters, each supplied through a slew rate limiter of the slope of the driving current and are respectively connected between the positive supply node of the output buffer and a negative (below ground potential) node and between the common ground node of the output buffer and a positive supply node. The negative voltage and the positive voltage on the nodes are at least equal to the absolute value of the threshold voltage of the natural or low threshold transistors.

Abstract translation: 输出CMOS缓冲器包括MOS增强晶体管，并且具有与最终缓冲级的互补对的增强型MOS晶体管的相反类型的导电性的晶体管并联连接的自然或低阈值晶体管的第二互补对。 一对自然或低阈值晶体管的栅极端子由相应的反相器控制，每个反相器通过驱动电流的斜率的转换速率限制器提供，并分别连接在输出缓冲器的正供电节点和负极（下面） 接地电位）节点和输出缓冲器的公共接地节点和正电源节点之间。 节点上的负电压和正电压至少等于自然或低阈值晶体管的阈值电压的绝对值。

公开(公告)号：US20080007295A1

公开(公告)日：2008-01-10

申请号：US11807150

申请日：2007-05-25

Applicant: Kalpendu Shastri

Inventor： Kalpendu Shastri

IPC: H03K19/096

CPC classification number: H03K19/09429

Abstract: A CMOS driver circuit is configured to provide a tri-state condition after a predetermined number of like-valued data bits have been transmitted, reducing the presence of intersymbol interference (ISI) along a transmission channel. In situations where the transmission channel is bandwidth-limited, the use of the tri-stating technique allows for the complete transition to the supply rails during the given bit period.

Abstract translation: CMOS驱动器电路被配置为在已经发送了预定数量的类似值的数据位之后提供三态条件，从而减少了沿着传输信道的符号间干扰（ISI）的存在。 在传输信道受带宽限制的情况下，三态技术的使用允许在给定位周期期间完全转换到电源轨。

公开(公告)号：US20070176633A1

公开(公告)日：2007-08-02

申请号：US11405524

申请日：2006-04-18

Applicant: Yukihito Kawabe

Inventor： Yukihito Kawabe

IPC: H03K19/00

CPC classification number: H03K19/09429 ,  H03K19/00361

Abstract: An output circuit including: a tri-state output circuit capable of outputting high-impedance state, high-level state, and low-level state, in which the high-level state and low-level state are low-impedance state, and switching the high-impedance state and the low-impedance state in accordance with a first control signal; and a delay circuit outputting the first control signal to the tri-state output circuit by inputting a second control signal and delaying the second control signal so that timing delay time of the second control signal switching the high-impedance state to the low-impedance state is longer than the timing delay time of the second control signal switching the low-impedance state to the high-impedance state, is provided.

Abstract translation: 一种输出电路，包括：能够输出高电平状态和低电平状态为低阻态的高阻抗状态，高电平状态和低电平状态的三态输出电路，以及开关 根据第一控制信号的高阻抗状态和低阻抗状态; 以及延迟电路，通过输入第二控制信号并延迟第二控制信号将第一控制信号输出到三态输出电路，使得第二控制信号的定时延迟时间将高阻抗状态切换到低阻态 比将低阻抗状态切换到高阻抗状态的第二控制信号的定时延迟时间长。