公开(公告)号：US20140285237A1

公开(公告)日：2014-09-25

申请号：US14296283

申请日：2014-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Greg King

IPC: H03K19/0948 ,  H03K19/003 ,  H03K19/094

CPC classification number: H03K19/0948 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1096 ,  H03K19/00315 ,  H03K19/09429

Abstract: Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node.

Abstract translation: 存储器，驱动器电路和用于响应于输入信号产生输出信号的方法。 一个这样的驱动器电路包括输入级和输出级。 输入级接收输入信号并提供相对于输入信号具有延迟的延迟输入信号。 输出级接收延迟的输入信号，并进一步接收输入信号的补码。 响应于具有第一逻辑电平的输入信号的补码，输出级将输出节点耦合到第一电压，并且响应于具有第二逻辑电平的输入信号的补码将输出耦合到第二电压。 响应于接收延迟的输入信号，输出级进一步使输出与第一或第二电压分离，以在输出节点处提供高阻抗。

公开(公告)号：US09735780B2

公开(公告)日：2017-08-15

申请号：US14296283

申请日：2014-06-04

Applicant: Micron Technology, Inc.

Inventor： Greg King

IPC: H03K19/0948 ,  G11C7/10 ,  H03K19/003 ,  H03K19/094

CPC classification number: H03K19/0948 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1096 ,  H03K19/00315 ,  H03K19/09429

Abstract: Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node.