公开(公告)号：US20110140223A1

公开(公告)日：2011-06-16

申请号：US12951700

申请日：2010-11-22

申请人： Noriyuki MIURA

发明人： Noriyuki MIURA

IPC分类号： H01L31/02

CPC分类号： H01L27/1446 ,  H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

摘要： A light detecting apparatus includes an SOI substrate. In the SOI substrate, a semiconductor layer and a silicon substrate are laminated via an insulating layer. The semiconductor layer has a light receiving unit and a circuit unit formed therein. The light detecting apparatus also includes an interlayer insulating film formed on a first main surface of the SOI substrate. The light detecting apparatus also includes a front surface circuit wiring embedded in the interlayer insulating film. The light detecting apparatus also includes a front surface pseudo-wiring having a grid unit. The grid unit has at least one opening allowing passage of a light of a predetermined wavelength range to the light receiving unit. The light detecting apparatus also includes a rear surface circuit wiring and a rear surface pseudo-wiring formed on a second main surface of the SOI substrate. The light detecting apparatus also includes a penetration circuit wiring that connects the front surface circuit wiring to the rear surface circuit wiring. The light detecting apparatus also includes a penetration pseudo-wiring that electrically connects the front surface pseudo-wiring to the rear surface pseudo-wiring. The light receiving unit is surrounded by the front surface pseudo-wiring, the rear surface pseudo-wiring, and the penetration pseudo-wiring.

摘要翻译： 光检测装置包括SOI衬底。 在SOI衬底中，通过绝缘层层叠半导体层和硅衬底。 半导体层具有形成在其中的光接收单元和电路单元。 光检测装置还包括形成在SOI衬底的第一主表面上的层间绝缘膜。 光检测装置还包括嵌入在层间绝缘膜中的前表面电路布线。 光检测装置还包括具有栅格单元的正面伪布线。 栅格单元具有至少一个允许预定波长范围的光通过光接收单元的开口。 光检测装置还包括形成在SOI衬底的第二主表面上的后表面电路布线和后表面伪布线。 光检测装置还包括将前表面电路布线连接到后表面电路布线的穿透电路布线。 光检测装置还包括将前表面伪布线电连接到后表面伪布线的穿透假布线。 光接收单元被前表面伪布线，后表面伪布线和穿透伪布线包围。

公开(公告)号：US20110133291A1

公开(公告)日：2011-06-09

申请号：US12915084

申请日：2010-10-29

申请人： Mayumi Shibata

发明人： Mayumi Shibata

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L27/0883 ,  H01L21/823412 ,  H01L21/823456

摘要： Disclosed is a fabrication method which includes: forming a first gate electrode and a second gate electrode which cross over an active region, the overall width of the second gate electrode being less than that of the first gate electrode; ion-implanting dopants into the active region at an oblique angle using the first and second gate electrodes as a mask for ion-implantation, thereby to form separated doped regions on opposite sides of the first gate electrode and to form a continuous doped region extending from one of opposite sides of the second gate electrode to the other.

摘要翻译： 公开了一种制造方法，其包括：形成与有源区交叉的第一栅电极和第二栅电极，第二栅电极的总宽度小于第一栅电极的总宽度; 使用第一和第二栅电极作为离子注入的掩模以倾斜角离子注入有源区，从而在第一栅电极的相对侧上形成分离的掺杂区，并形成从 第二栅电极的相对侧之一到另一个。

公开(公告)号：US07955963B2

公开(公告)日：2011-06-07

申请号：US10798482

申请日：2004-03-12

申请人： Akira Takahashi

发明人： Akira Takahashi

IPC分类号： H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/32137 ,  H01L21/82385

摘要： The present invention provides a device having an N type polysilicon gate and a P type polysilicon gate disposed therein, wherein when both gates are simultaneously etched, they are disposed in such a manner that the area of a non-doped polysilicon gate corresponding to a dummy electrode becomes larger than the total area of the N type and P type doped polysilicon gates, thereby causing non-doped polysilicon to become dominant over doped polysilicon, whereby the polysilicon gates are dry-etched.

摘要翻译： 本发明提供了一种具有N型多晶硅栅极和设置在其中的P型多晶硅栅极的器件，其中当两个栅极同时被蚀刻时，它们被设置成使得非掺杂多晶硅栅极的面积对应于虚拟 电极变得大于N型和P型掺杂多晶硅栅极的总面积，从而使非掺杂多晶硅在掺杂多晶硅上成为主导，由此多晶硅栅极被干蚀刻。

公开(公告)号：US20110128019A1

公开(公告)日：2011-06-02

申请号：US12926275

申请日：2010-11-05

申请人： Naotaka Saito

发明人： Naotaka Saito

IPC分类号： G01R27/08 ,  H04R1/10

CPC分类号： H04R5/04 ,  G01R31/043 ,  H01R13/703

摘要： This method is applied to a dual-use jack of an electronic device. Either a headphone plug or a line output plug is inserted into the dual-use jack. The method determines the type of a plug connected to the dual-use jack when the plug is inserted into the dual-use jack. The determination is made based on a load resistance of the plug connected to the jack. The method includes feeding an electric current through the load resistance in a first direction. The method compares a voltage across the load resistance to a reference voltage and determines the type of the plug in use. The method also includes feeding an electric current through the load resistance in a second direction. This electric current can reduce or eliminate a pop-noise when the plug type is determined. The second direction is different from the first direction.

摘要翻译： 该方法适用于电子设备的双重使用插座。 将耳机插头或线路输出插头插入双用途插孔。 当插头插入双用途插孔时，该方法确定连接到双用插孔的插头类型。 基于连接到千斤顶的插头的负载电阻进行确定。 该方法包括沿第一方向馈送电流通过负载电阻。 该方法将负载电阻与参考电压进行比较，并确定使用中的插头类型。 该方法还包括在第二方向上馈送电流通过负载电阻。 当确定插头类型时，该电流可以减少或消除爆音。 第二个方向与第一个方向不同。

公开(公告)号：US07949697B2

公开(公告)日：2011-05-24

申请号：US11882356

申请日：2007-08-01

申请人： Kenichi Handa

发明人： Kenichi Handa

IPC分类号： G06F15/00

CPC分类号： G06F7/764

摘要： A bit field operation circuit has a first shift unit, a mask shift amount control circuit, a second shift unit, a logic operation unit, and a selection unit. The first shift unit outputs a first intermediate data based on a first control signal. The mask shift amount control circuit outputs a mask shift control signal in accordance with a mask shift amount. The second shift unit outputs a second intermediate data based on a mask shift control signal. The third shift unit outputs a third intermediate data based on the first control signal. The logic operation unit performs logical operation of the second intermediate data and the third intermediate data, and outputs a mask selection data. The selection unit selects either one of the first intermediate data or the second input data based on the mask selection data to output as output data.

摘要翻译： 位场运算电路具有第一移位单元，掩码移位量控制电路，第二移位单元，逻辑运算单元和选择单元。 第一移位单元基于第一控制信号输出第一中间数据。 掩模偏移量控制电路根据掩模偏移量输出掩模移位控制信号。 第二移位单元基于掩码移位控制信号输出第二中间数据。 第三移位单元基于第一控制信号输出第三中间数据。 逻辑运算单元执行第二中间数据和第三中间数据的逻辑运算，并输出掩模选择数据。 选择单元基于掩模选择数据选择第一中间数据或第二输入数据中的任一个作为输出数据输出。

公开(公告)号：US07947514B2

公开(公告)日：2011-05-24

申请号：US12076219

申请日：2008-03-14

申请人： Koichi Kishiro ,  Kouji Nasu

发明人： Koichi Kishiro ,  Kouji Nasu

IPC分类号： H01L21/66

CPC分类号： H01L22/14 ,  H01L24/06 ,  H01L27/1203 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/4903 ,  H01L2924/00014

摘要： A semiconductor device production process includes forming, on a prepared SOI wafer, semiconductor functional devices and substrate contacts. The substrate contacts connect to a support substrate of the SOI wafer. The semiconductor device production process also includes forming a pattern that connects the substrate contacts to external connection pads formed on the semiconductor functional devices such that the external connection pads are not connected to each other. The semiconductor device production process also includes measuring conductivity between the external connection pads.

摘要翻译： 半导体器件制造方法包括在准备的SOI晶片上形成半导体功能器件和衬底触点。 衬底触点连接到SOI晶片的支撑衬底。 半导体器件制造工艺还包括形成将衬底触点连接到形成在半导体功能器件上的外部连接焊盘的图案，使得外部连接焊盘彼此不连接。 半导体器件制造工艺还包括测量外部连接焊盘之间的导电性。

公开(公告)号：US07938005B2

公开(公告)日：2011-05-10

申请号：US12607407

申请日：2009-10-28

申请人： Shunji Ichikawa

发明人： Shunji Ichikawa

IPC分类号： G01P15/08

CPC分类号： G01P1/023 ,  G01P15/123 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： An acceleration sensor chip package includes an acceleration sensor chip; a sensor control chip; a re-wiring layer; an outer terminal; a sealing portion; and a substrate. The acceleration sensor chip includes a frame portion; a movable structure; a detection element; and an electrode pad electrically. The re-wiring layer has a wiring portion connected to the electrode pad. The electrode pad is electrically connected to a conductive bump. The sensor control chip has a sensor control electrode pad electrically connected to the conductive bump. The outer terminal is connected to the wiring portion and disposed in the outer region. The sealing portion seals the sensor control chip, the electrode pad, and the re-wiring layer, so that the movable structure is movable. The substrate is attached to the acceleration sensor chip to seal an opening portion.

摘要翻译： 加速度传感器芯片封装包括加速度传感器芯片; 传感器控制芯片; 重新布线层; 外部终端; 密封部分; 和基材。 加速度传感器芯片包括框架部分; 可移动结构; 检测元件; 和电极垫。 再布线层具有连接到电极焊盘的布线部分。 电极焊盘电连接到导电凸块。 传感器控制芯片具有电连接到导电凸块的传感器控制电极焊盘。 外部端子连接到布线部分并且设置在外部区域中。 密封部密封传感器控制芯片，电极焊盘和再布线层，使得可移动结构是可移动的。 衬底附接到加速度传感器芯片以密封开口部分。

公开(公告)号：US07937846B2

公开(公告)日：2011-05-10

申请号：US12073971

申请日：2008-03-12

申请人： Nobuo Ozawa

发明人： Nobuo Ozawa

IPC分类号： G01C9/02 ,  H01H35/02 ,  H01H11/04

CPC分类号： G01C9/02

摘要： An inclination position sensor where, on a substrate on which wires are formed, plural electrodes electrically connected to the wires are disposed, a conductive ball that can simultaneously contact at least two of the plural electrodes is disposed, an enclosure that covers the plural electrodes and the conductive ball is disposed, and a circular arc is formed in places of the electrodes that contact the conductive ball.

摘要翻译： 一种倾斜位置传感器，其中，在形成有导线的基板上设置与导线电连接的多个电极，设置能同时接触多个电极中的至少两个的导电球，覆盖多个电极的外壳和 设置导电球，并且在与导电球接触的电极的位置处形成圆弧。

公开(公告)号：US07937607B2

公开(公告)日：2011-05-03

申请号：US11889860

申请日：2007-08-17

申请人： Masahiko Hayano ,  Yoshitaka Suzuki

发明人： Masahiko Hayano ,  Yoshitaka Suzuki

IPC分类号： H04L7/00 ,  G06F13/42

CPC分类号： G06F1/12 ,  G06F5/06

摘要： An asynchronous data holding circuit including a source synchronizer which acquires an enable signal synchronized with a destination clock, in response to a rising or falling edge of the enable signal, acquires the other one of the rising or falling edge of the enable signal in synchronization with a source clock, and outputs the enable signal, a first data holding unit which holds a data signal from the source, in response to the enable signal from the source synchronizer and the source clock, a destination synchronizer which outputs the enable signal from the source synchronizer, in synchronization with the destination clock, and a second data holding unit which holds the data signal in the first data holding unit in response to the enable signal from the destination synchronizer and the destination clock, is provided.

摘要翻译： 包括源同步器的异步数据保持电路，其响应于使能信号的上升沿或下降沿，获取与目的时钟同步的使能信号，同步地获取使能信号的上升沿或下降沿中的另一个 源时钟，并且响应于来自源同步器和源时钟的使能信号，输出启动信号，第一数据保持单元，其保存来自源的数据信号;目的同步器，其从源输出使能信号 同步器，与目的地时钟同步，以及第二数据保持单元，其响应于来自目的地同步器和目的地时钟的使能信号而保持第一数据保持单元中的数据信号。

公开(公告)号：US20110090752A1

公开(公告)日：2011-04-21

申请号：US12923981

申请日：2010-10-19

申请人： Waichiro Fujieda

发明人： Waichiro Fujieda

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C17/123

摘要： There is provided a semiconductor memory device including: plural memory cells; a selection signal outputting section; a first precharging section that precharges a potential of a data line that outputs, to an exterior, a signal of a level corresponding to data stored in the memory cell; and a bit line selecting section that has, per bit line, a bit line selecting section that comprises (1) a second precharging section, (2) a potential lowering section, and (3) a third precharging section connected to the bit line selection line and the bit line between the second precharging section and a connection point at which the potential lowering section is connected to the bit line, and when the non-selection signal is inputted, the third precharging section precharges the bit line between the second precharging section and the connection point at which the potential lowering section is connected to the bit line.

摘要翻译： 提供了一种半导体存储器件，包括：多个存储单元; 选择信号输出部; 预先充电数据线的电位的第一预充电部分，其向外部输出与存储在存储单元中的数据相对应的电平的信号; 以及位线选择部分，每个位线具有位线选择部分，该位线选择部分包括：（1）第二预充电部分，（2）电位降低部分;以及（3）连接到位线选择的第三预充电部分 以及第二预充电部分和电位降低部分连接到位线的连接点之间的位线，并且当输入非选择信号时，第三预充电部分预充电第二预充电部分之间的位线 以及电位降低部分连接到位线的连接点。