公开(公告)号：US10916595B2

公开(公告)日：2021-02-09

申请号：US16376608

申请日：2019-04-05

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Junhyun Park ,  Sunkwang Kim ,  Kangmoon Jo

IPC: H01L27/32 ,  H01L51/52 ,  H01L51/00

Abstract: A display device includes a substrate, a first insulating layer disposed on the substrate, a through portion passing through the substrate and the first insulating layer, a display unit disposed on the first insulating layer and including a plurality of pixels surrounding at least a portion of the through portion, and a dummy pixel unit. Each pixel includes a light-emitting element including a pixel electrode and an opposite electrode facing each other, and an emission layer disposed between the pixel electrode and the opposite electrode. The dummy pixel unit includes a plurality of dummy pixels disposed between the through portion and the display unit, and including a metal pattern including a same material as the pixel electrode. The dummy pixels are disposed adjacent to the display unit.

公开(公告)号：US20200295310A1

公开(公告)日：2020-09-17

申请号：US16793394

申请日：2020-02-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sungjae Moon ,  Dongwoo Kim ,  Junhyun Park ,  Kangmoon Jo

IPC: H01L51/52 ,  H01L27/32

Abstract: A display device includes a first substrate including a display area and a peripheral area outside the display area, pixels arranged in the display area and each including an emission area defined by a non-emission area, a thin-film encapsulation layer covering the pixels and including at least one inorganic encapsulation layer and at least one organic encapsulation layer, a pattern layer above the thin-film encapsulation layer, the pattern layer including a first light-blocking pattern shielding at least a portion of the non-emission area, and a second substrate facing the first substrate and including a second light-blocking pattern shielding at least a portion of the non-emission area.

公开(公告)号：US20200258920A1

公开(公告)日：2020-08-13

申请号：US16784743

申请日：2020-02-07

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Dongwoo Kim ,  Junhyun Park ,  Sungjae Moon ,  Ansu Lee ,  Kangmoon Jo

IPC: H01L27/12 ,  H01L27/32

Abstract: A display panel includes a first transistor that contains oxide, a capacitor that includes a first electrode and a second electrode, a light emitting element connected to the capacitor and the first transistor, and an additional control electrode connected to the second electrode. The first and second electrodes are disposed on different layers from each other and are coupled to a first control electrode and a first output electrode, respectively, of the first transistor, and the light emitting element includes a light emitting layer. The additional control electrode overlap the first control electrode and the first semiconductor pattern, when viewed in a plan view. The additional control electrode and the second electrode are disposed on the same layer and form a single body.

公开(公告)号：US20190319212A1

公开(公告)日：2019-10-17

申请号：US16386187

申请日：2019-04-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Junhyun Park ,  Ansu Lee

IPC: H01L51/52 ,  H01L27/32

Abstract: A display panel includes an insulating substrate in which at least one hole is defined, wherein the insulating substrate comprises a hole area in which the hole is defined, a display area surrounding the hole area, and a peripheral area adjacent to the display area, a plurality of pixels in the display area, a plurality of main signal lines in the display area and electrically connected to the pixels, and a plurality of sub-signal lines in the hole area and electrically connected to the pixels, wherein the hole area comprises a line area which surrounds the hole and in which the sub-signal lines are located, and a compensation area between the line area and the display area in a plan view and configured to display a black color.

公开(公告)号：US10121439B2

公开(公告)日：2018-11-06

申请号：US15233851

申请日：2016-08-10

Applicant: Samsung Display Co., Ltd.

Inventor： Sunghwan Kim ,  Junhyun Park ,  Kyoungju Shin ,  Woongsik Choi

IPC: G09G3/36

Abstract: A display device includes: a display panel; and a gate driving circuit, a kth driving stage from among driving stages for outputting a kth gate signal from among gate signals, where k is a natural number of two or more, including: at least one output transistor including a control electrode connected to a first node, an input electrode to receive a clock signal, and an output electrode to output an output signal; a first control transistor to output an activation signal to the first node before the kth gate signal is outputted; a capacitor to boost a voltage of the first node after the activation signal is provided to the first node; second and third control transistors connected in series between the first node and a voltage input terminal; and a first intermediate node between the second control transistor and the third control transistor for receiving the output signal.

公开(公告)号：US09941143B2

公开(公告)日：2018-04-10

申请号：US14687080

申请日：2015-04-15

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Chanwoo Yang ,  Do-Hyun Kim ,  Jeongju Park ,  Junhyun Park ,  Doohyoung Lee ,  Xinxing Li

IPC: H01L29/786 ,  H01L21/467 ,  H01L29/66 ,  H01L21/4757 ,  H01L29/417 ,  H01L29/45 ,  H01L27/12

CPC classification number: H01L21/467 ,  H01L21/47573 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: A thin film transistor include a control electrode, a semiconductor layer on the control electrode, an input electrode, at least a portion of the input electrode being on the semiconductor layer, and an output electrode spaced apart from the input electrode, at least a portion of the output electrode being on the semiconductor layer. Each of the input electrode and the output electrode includes a wiring layer including a metal material, a dummy portion on a side part of the wiring layer, the dummy portion including an oxide of the metal material, and a protection layer on the wiring layer, the protection layer overlapping the wiring layer and the dummy portion.

公开(公告)号：US20170193947A1

公开(公告)日：2017-07-06

申请号：US15233851

申请日：2016-08-10

Applicant: Samsung Display Co., Ltd.

Inventor： Sunghwan Kim ,  Junhyun Park ,  Kyoungju Shin ,  Woongsik Choi

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/08

Abstract: A display device includes: a display panel; and a gate driving circuit, a kth driving stage from among driving stages for outputting a kth gate signal from among gate signals, where k is a natural number of two or more, including: at least one output transistor including a control electrode connected to a first node, an input electrode to receive a clock signal, and an output electrode to output an output signal; a first control transistor to output an activation signal to the first node before the kth gate signal is outputted; a capacitor to boost a voltage of the first node after the activation signal is provided to the first node; second and third control transistors connected in series between the first node and a voltage input terminal; and a first intermediate node between the second control transistor and the third control transistor for receiving the output signal.

公开(公告)号：US20170018245A1

公开(公告)日：2017-01-19

申请号：US15080515

申请日：2016-03-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Junhyun Park ,  Kyoung-ju Shin

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G3/20 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2310/0251 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28

Abstract: A gate driving circuit includes driving stages to provide gate signals to gate lines of a display panel, a k-th driving stage (where k is a natural number greater than 2) of the driving stages including an output unit to output a k-th gate signal to a k-th gate line and a k-th carry signal to a k-th carry terminal in response to a voltage of a first node, a control unit to control a potential of the first node, a pull-down unit to pull down the k-th gate line and the k-th carry terminal to a ground voltage in response to a (k+1)-th carry signal, and a reset unit to reset the voltage of the first node to the ground voltage in response to the reset signal. The reset unit receives one of the k-th gate signal and the k-th carry signal as a feedback signal.

Abstract translation: 栅极驱动电路包括用于向显示面板的栅极线提供栅极信号的驱动级，包括输出单元的驱动级的第k级驱动级（其中k为大于2的自然数），以输出第k级 响应于第一节点的电压，控制第一节点的电位的控制单元，第一节点的电位的控制单元，第一节点的电位的控制单元，下拉单元 以响应于第（k + 1）个进位信号将第k个栅极线和第k个进位端子下拉到地电压;以及复位单元，用于将第一个节点的电压重新设置为接地电压 响应于复位信号。 复位单元接收第k个门信号和第k个进位信号中的一个作为反馈信号。

公开(公告)号：US20160300852A1

公开(公告)日：2016-10-13

申请号：US14927269

申请日：2015-10-29

Applicant: Samsung Display Co., Ltd.

Inventor： Junhyun Park ,  Sunghwan Kim ,  Kyoungju Shin ,  Chongchul Chai

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136236 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: Provided is a method of manufacturing TFT substrate, the method including: forming a first conductive layer and a gate electrode; forming a gate insulating layer covering the first conductive layer and the gate electrode; forming a first contact hole exposing the first conductive layer through the gate insulating layer; forming, on the gate insulating layer of a pixel area, an oxide semiconductor pattern comprising a first region which is conductive, a second region which is conductive, and a third region between the first region and the second region; forming a source electrode contacting the first region of the oxide semiconductor pattern, a drain electrode contacting the second region of the oxide semiconductor pattern and a second conductive layer contacting the first conductive layer on a non-pixel area. Each of the first region and the second region overlaps the gate electrode.

Abstract translation: 提供一种制造TFT基板的方法，该方法包括：形成第一导电层和栅电极; 形成覆盖所述第一导电层和所述栅电极的栅极绝缘层; 形成通过所述栅极绝缘层暴露所述第一导电层的第一接触孔; 在像素区域的栅极绝缘层上形成氧化物半导体图案，该氧化物半导体图案包括导电的第一区域，导电的第二区域和位于第一区域与第二区域之间的第三区域; 形成与氧化物半导体图案的第一区域接触的源电极，与氧化物半导体图案的第二区域接触的漏电极和在非像素区域上接触第一导电层的第二导电层。 第一区域和第二区域中的每一个与栅电极重叠。