公开(公告)号：US20170083997A1

公开(公告)日：2017-03-23

申请号：US14857303

申请日：2015-09-17

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Rexford Alan Hill ,  Shambhoo Khandelwal

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G06F12/0207 ,  G06F2212/401 ,  G06T1/20 ,  G06T11/40 ,  G06T2210/08

Abstract: A computing device may allocate a plurality of blocks in the memory, wherein each of the plurality of blocks is of a uniform fixed size in the memory. The computing device may further store a plurality of bandwidth-compressed graphics data into the respective plurality of blocks in the memory, wherein one or more of the plurality of bandwidth-compressed graphics data each has a size that is smaller than the fixed size. The computing device may further store data associated with the plurality of bandwidth-compressed graphics data into unused space of one or more of the plurality of blocks that contains the respective one or more of the plurality of bandwidth-compressed graphics data.

公开(公告)号：US09483861B2

公开(公告)日：2016-11-01

申请号：US13841584

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Christopher Paul Frascati ,  Avinash Seetharamaiah ,  Andrew Evan Gruber

IPC: G06T15/00 ,  G06T17/20

CPC classification number: G06T15/005

Abstract: This disclosure describes techniques for using bounding regions to perform tile-based rendering with a graphics processing unit (GPU) that supports an on-chip, tessellation-enabled graphics rendering pipeline. Instead of generating binning data based on rasterized versions of the actual primitives to be rendered, the techniques of this disclosure may generate binning data based on a bounding region that encompasses one or more of the primitives to be rendered. Moreover, the binning data may be generated based on data that is generated by at least one tessellation processing stage of an on-chip, tessellation-enabled graphics rendering pipeline that is implemented by the GPU. The techniques of this disclosure may, in some examples, be used to improve the performance of an on-chip, tessellation-enabled GPU when performing tile-based rendering without sacrificing the quality of the resulting rendered image.

Abstract translation: 本公开描述了使用边界区域来执行基于瓦片的渲染的技术，该图形处理单元（GPU）支持片上，镶嵌的图形渲染流水线。 基于要渲染的实际原语的光栅化版本而不是生成合并数据，本公开的技术可以基于包含要呈现的一个或多个基元的边界区域来生成合并数据。 此外，可以基于由GPU实现的片上，镶嵌使能的图形呈现流水线的至少一个镶嵌处理阶段生成的数据来生成合并数据。 在一些示例中，本公开的技术可以用于在不牺牲所得到的渲染图像的质量的情况下执行基于图块的渲染时，提高片上，镶嵌功能的GPU的性能。

公开(公告)号：US09412197B2

公开(公告)日：2016-08-09

申请号：US13830145

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Andrew Evan Gruber ,  Donghyun Kim

IPC: G06T15/80 ,  G06T15/00

CPC classification number: G06T15/80 ,  G06T15/00 ,  G06T15/005

Abstract: Aspects of this disclosure generally relate to a process for rendering graphics that includes performing, with a hardware shading unit of a graphics processing unit (GPU) designated for vertex shading, vertex shading operations to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit is configured to receive a single vertex as an input and generate a single vertex as an output. The process also includes performing, with the hardware shading unit of the GPU, a geometry shading operation to generate one or more new vertices based on one or more of the vertex shaded vertices, wherein the geometry shading operation operates on at least one of the one or more vertex shaded vertices to output the one or more new vertices.

Abstract translation: 本公开的方面通常涉及用于渲染图形的处理，其包括使用指定为顶点着色的图形处理单元（GPU）的硬件阴影单元执行遮蔽输入顶点的顶点着色操作，以便输出顶点着色顶点，其中 硬件单元被配置为接收单个顶点作为输入并且生成单个顶点作为输出。 该过程还包括利用GPU的硬件着色单元执行基于顶点着色顶点中的一个或多个以生成一个或多个新顶点的几何阴影操作，其中，几何阴影操作对一个 或多个顶点着色顶点，以输出一个或多个新顶点。

公开(公告)号：US20160171644A1

公开(公告)日：2016-06-16

申请号：US14566423

申请日：2014-12-10

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F13/28 ,  G06T1/20 ,  G06T2200/28 ,  Y02D10/14

Abstract: This disclosure describes techniques for processing unaligned block transfer (BLT) commands. The techniques of this disclosure may involve converting an unaligned BLT command into multiple aligned BLT commands, where the multiple aligned BLT commands may collectively produce the same resulting memory state as that which would have been produced by the unaligned BLT command. The techniques of this disclosure may allow the benefits of relatively low-power GPU-accelerated BLT processing may be achieved for unaligned BLT commands without requiring a CPU to pre-process and/or post-process the underlying unaligned surfaces. In this way, the performance and/or power consumption associated with processing unaligned BLT commands in an alignment-constrained GPU-based system may be improved.

Abstract translation: 本公开描述了用于处理未对齐块传输（BLT）命令的技术。 本公开的技术可以涉及将未对齐的BLT命令转换成多个对准的BLT命令，其中多个对齐的BLT命令可以共同地产生与由未对齐的BLT命令产生的相同的结果存储器状态。 本公开的技术可以允许对于未对齐的BLT命令可以实现相对低功率的GPU加速的BLT处理的优点，而不需要CPU预处理和/或后处理底层的未对准的表面。 以这种方式，可以提高与基于对准约束的基于GPU的系统中处理未对齐的BLT命令相关联的性能和/或功耗。

公开(公告)号：US20160132987A1

公开(公告)日：2016-05-12

申请号：US14537589

申请日：2014-11-10

Applicant: QUALCOMM Incorporated

Inventor： Liang Li ,  Andrew Evan Gruber ,  Guofang Jiao ,  Zhenyu Qi ,  Gregory Steve Pitarys ,  Scott William Nolan

IPC: G06T1/20 ,  G09G5/18

CPC classification number: G06T1/20 ,  G09G5/18 ,  G09G2330/022

Abstract: This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.

Abstract translation: 本公开描述了被配置为处理图形数据的装置。 该装置可以包括被配置为在当前图形数据集上执行一个或多个功能的固定硬件流水线。 固定硬件管线可以包括多个级，包括多个级的可旁路部分。 该装置还可以包括快速电路，其被配置为将当前图形数据集合围绕多个级的可旁路部分路由，以及位于多个级的可旁路部分之前的控制器，所述控制器被配置为选择性地路由当前集合 的图形数据提供给多个阶段的快捷电路或可旁路部分中的一个。

公开(公告)号：US20160054998A1

公开(公告)日：2016-02-25

申请号：US14462932

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Lin Chen ,  Andrew Evan Gruber ,  Chihong Zhang ,  Chun Yu

IPC: G06F9/30 ,  G06T1/20

CPC classification number: G06F9/30098 ,  G06F8/441 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/3828 ,  G06F9/3859 ,  G06T1/20 ,  G06T2200/28

Abstract: Techniques are described in which an indication is included to indicate a last use of an intermediate value generated as part of determining a final value is not be stored in a general purpose register (GPR). A processing unit avoids storing the intermediate value in the GPR based on the indication because the intermediate value is no longer needed for determining the final value.

Abstract translation: 描述了其中包括指示以指示作为确定最终值的一部分而生成的中间值的最后使用的指示不被存储在通用寄存器（GPR）中的技术。 处理单元基于指示，避免将中间值存储在GPR中，因为不再需要中间值来确定最终值。

公开(公告)号：US09230518B2

公开(公告)日：2016-01-05

申请号：US14023170

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Christopher Paul Frascati ,  Murat Balci ,  Avinash Seetharamaiah ,  Andrew Evan Gruber ,  Alexei Vladimirovich Bourd

IPC: G06T1/00 ,  G06T15/00 ,  G06F15/00 ,  G09G5/399 ,  G06T1/20 ,  G06F9/46 ,  G06T1/60

CPC classification number: G09G5/399 ,  G06F9/46 ,  G06F9/4843 ,  G06F2209/483 ,  G06F2209/509 ,  G06T1/20 ,  G06T1/60

Abstract: This disclosure presents techniques and structures for preemption at arbitrary control points in graphics processing. A method of graphics processing may comprise executing commands in a command buffer, the commands operating on data in a read-modify-write memory resource, double buffering the data in the read-modify-write memory resource, such that a first buffer stores original data of the read-modify-write memory resource and a second buffer stores any modified data produced by executing the commands in the command buffer, receiving a request to preempt execution of the commands in the command buffer before completing all commands in the command buffer, and restarting execution of the commands at the start of the command buffer using the original data in the first buffer.

Abstract translation: 本公开提供在图形处理中的任意控制点处的抢占的技术和结构。 图形处理的方法可以包括在命令缓冲器中执行命令，操作在读 - 修改 - 写存储器资源中的数据的命令，双重缓冲读 - 修改 - 写存储器资源中的数据，使得第一缓冲器存储原始 读取 - 修改 - 写入存储器资源的数据和第二缓冲器存储通过执行命令缓冲器中的命令而产生的任何修改的数据，在完成命令缓冲器中的所有命令之前，接收到抢占执行命令缓冲器中的命令的请求， 并使用第一缓冲器中的原始数据重新启动命令缓冲区开始处的命令。

公开(公告)号：US20150379663A1

公开(公告)日：2015-12-31

申请号：US14316275

申请日：2014-06-26

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Tao Wang ,  Chunhui Mei ,  Gang Zhong ,  Feng Ge

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T15/005 ,  G09G5/363 ,  G09G2340/0407 ,  G09G2360/122

Abstract: In an example, a method for rendering graphics data includes rendering pixels of a first bin of a plurality of bins, wherein the pixels of the first bin are associated with a first portion of an image, and rendering, to the first bin, one or more pixels that are located outside the first portion of the image and associated with a second, different bin of the plurality of bins. The method also includes rendering the one or more pixels associated with the second bin to the second bin, such that the one or more pixels are rendered to both the first bin and the second bin.

Abstract translation: 在一个示例中，用于渲染图形数据的方法包括渲染多个箱的第一仓的像素，其中第一仓的像素与图像的第一部分相关联，并且向第一仓中呈现一个或 更多的像素位于图像的第一部分之外并且与多个箱的第二不同仓相关联。 该方法还包括将与第二仓相关联的一个或多个像素渲染到第二仓，使得一个或多个像素被渲染到第一仓和第二仓。

公开(公告)号：US12249021B2

公开(公告)日：2025-03-11

申请号：US17934869

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Piyush Gupta ,  Pavan Kumar Akkaraju ,  Alexei Vladimirovich Bourd ,  Andrew Evan Gruber

IPC: G06T15/06 ,  G06T17/00 ,  G06T17/10

Abstract: Systems and techniques are provided for accelerated ray tracing. For instance, a process can include obtaining a hierarchical acceleration data structure that includes a plurality of primitives of a scene object and obtaining a respective information value associated with each primitive included in the plurality of primitives. A sort order can be determined for two or more nodes included in a same level of the hierarchical acceleration data structure at least in part by sorting the two or more nodes based on a respective sorting parameter value determined for each respective node of the two or more nodes. Each respective sorting parameter value can be determined based on at least one information value associated with one or more primitives included in a sub-tree of each respective node of the two or more nodes. The hierarchical acceleration data structure can be traversed using the sort order.

公开(公告)号：US12229215B2

公开(公告)日：2025-02-18

申请号：US18487918

申请日：2023-10-16

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Gang Zhong ,  Fei Wei ,  Yibin Zhang ,  Jing Han ,  Hongjiang Shang ,  Elina Kamenetskaya ,  Minjie Huang ,  Alexei Vladimirovich Bourd ,  Chun Yu ,  Andrew Evan Gruber ,  Eric Demers

IPC: G06F17/16 ,  G06F7/57 ,  G06F9/30 ,  G06F9/38

Abstract: The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.