公开(公告)号：US11935816B2

公开(公告)日：2024-03-19

申请号：US17839828

申请日：2022-06-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih ,  Jheng-Ting Jhong

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L21/3065

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/32 ,  H01L24/83 ,  H01L21/30655 ,  H01L2224/32145 ,  H01L2224/83203 ,  H01L2224/83896

Abstract: The present disclosure provides a semiconductor device, a semiconductor assembly and method of manufacturing the semiconductor assembly. The semiconductor device includes a substrate, a conductive feature in the substrate, an isolation liner between the substrate and the conductive feature, and a main component in the substrate. The conductive feature includes first to third blocks. The first block has a uniform first critical dimension, wherein the main component is disposed around the first block. The second block has a uniform second critical dimension greater than the first critical dimension. The third block is interposed between the first block and the second block and has varying third critical dimensions.

公开(公告)号：US11876079B2

公开(公告)日：2024-01-16

申请号：US17534836

申请日：2021-11-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541

Abstract: The provides a method for fabricating a semiconductor device including performing a bonding process to bond a second die onto a first die including a pad layer, forming a through-substrate opening along the second die and extending to the pad layer in the first die, conformally forming an isolation layer in the through-substrate opening, performing a punch etch process to remove a portion of the isolation layer and expose a portion of a top surface of the pad layer, performing an isotropic etch process to form a recessed space extending from the through substrate opening and in the pad layer, conformally forming a barrier layer in the through-substrate opening and the recessed space, and forming a filler layer in the through-substrate opening and the recessed space.

公开(公告)号：US11798879B2

公开(公告)日：2023-10-24

申请号：US17529487

申请日：2021-11-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L23/522 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/5226 ,  H01L21/56 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192

Abstract: A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern. The semiconductor device also includes a first passivation layer over the conductive pattern; a second passivation layer over the first passivation layer; an interconnect structure disposed over the conductive pattern and in the first passivation layer and the second passivation layer; and an interconnect liner disposed between the interconnect structure and the conductive pattern and surrounding the interconnect structure, wherein inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern.

公开(公告)号：US11735499B2

公开(公告)日：2023-08-22

申请号：US17529520

申请日：2021-11-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang ,  Shing-Yih Shih

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/53238 ,  H01L24/80 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a second mask layer positioned on the first mask layer, a conductive filler layer positioned penetrating the second mask layer, the first mask layer, and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die, between the conductive filler layer and the second die, and between the conductive filler layer and the first mask layer, and protection layers positioned between the conductive filler layer and the second mask layer and between the conductive filler layer and the first mask layer, and covering upper portions of the isolation layers.

公开(公告)号：US11728316B2

公开(公告)日：2023-08-15

申请号：US17746030

申请日：2022-05-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: The present application provides a method for fabricating a semiconductor device. The method includes providing a carrier substrate, forming through semiconductor vias in the carrier substrate for thermally conducting heat, forming a bonding layer on the carrier substrate, providing a first die structure including through semiconductor vias, forming an intervening bonding layer on the first die structure, bonding the first die structure onto the bonding layer through the intervening bonding layer, and bonding a second die structure onto the first die structure. The carrier substrate, the through semiconductor vias, and the bonding layer together configure a carrier structure. The second die structure and the first die structure are electrically coupled by the through semiconductor vias.

公开(公告)号：US11462453B2

公开(公告)日：2022-10-04

申请号：US16926281

申请日：2020-07-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang ,  Shing-Yih Shih

IPC: H01L21/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/18 ,  H01L23/29 ,  H01L21/311

Abstract: The present application discloses a semiconductor device with protection layers for reducing the metal to silicon leakage and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a conductive filler layer positioned along the first mask layer and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die and between the conductive filler layer and the second die, and protection layers positioned between the conductive filler layer and the first mask layer and covering upper portions of the isolation layers.

公开(公告)号：US20220148995A1

公开(公告)日：2022-05-12

申请号：US17093974

申请日：2020-11-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih ,  Tse-Yao Huang

IPC: H01L23/00

Abstract: A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.

公开(公告)号：US11309312B2

公开(公告)日：2022-04-19

申请号：US16702884

申请日：2019-12-04

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L27/108 ,  G11C5/06 ,  H01L27/11573 ,  H01L27/11582

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a center area and a peripheral area surrounding the center area, a first gate stack positioned on the peripheral area of the substrate, and an active column positioned in the center area of the substrate. A top surface of the first gate stack and a top surface of the active column are at a same vertical level.

公开(公告)号：US11239217B2

公开(公告)日：2022-02-01

申请号：US16833690

申请日：2020-03-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L25/10 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package.

公开(公告)号：US20220028734A1

公开(公告)日：2022-01-27

申请号：US17449951

申请日：2021-10-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih ,  Mao-Ying Wang ,  Hung-Mo Wu

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/522

Abstract: A semiconductor structure includes a semiconductor device, a conductive line, a dielectric layer and a redistribution layer (RDL). The conductive line is present over the semiconductor device. The dielectric layer is present over the conductive line. The RDL includes a conductive structure over the dielectric layer and a conductive via extending downwards from the conductive structure and through the dielectric layer. The conductive via comprises a bottom portion, a top portion, and a tapered portion between the bottom and top portions, wherein the tapered portion has a width variation greater than that of the bottom and top portions.