公开(公告)号：US09704563B2

公开(公告)日：2017-07-11

申请号：US14940073

申请日：2015-11-12

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C11/4093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data.

公开(公告)号：US09691468B2

公开(公告)日：2017-06-27

申请号：US14793569

申请日：2015-07-07

Applicant: INTEL CORPORATION

Inventor： Kuljit S. Bains

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618

Abstract: A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition.

公开(公告)号：US20170093400A1

公开(公告)日：2017-03-30

申请号：US14865866

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Alexey Kostinsky ,  Nadav Bonen

IPC: H03K19/0175 ,  G06F3/06 ,  G06F13/16

CPC classification number: H03K19/017545 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1668

Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.

公开(公告)号：US20170060680A1

公开(公告)日：2017-03-02

申请号：US14998059

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/401 ,  G11C29/42 ,  G11C29/52 ,  H03M13/095 ,  H03M13/6566

Abstract: A check bit read mode enables a memory device to provide internal check bits to an associated host. A memory controller of a memory subsystem can generate one or more read commands for memory devices of the memory subsystem. The read command can include address location information. The memory devices include memory arrays with memory locations addressable with the address location information. The memory locations have associated data and internal check bits, where the check bits are generated internally by the memory for error correction. If the memory device is configured for check bit read mode, in response to the read command, it sends the internal check bits associated with the identified address location. If the memory device is not configured check bit read mode, it returns the data in response to the read command without exposing the internal check bits.

Abstract translation: 检查位读取模式使存储器件能够向关联的主机提供内部校验位。 存储器子系统的存储器控​​制器可以为存储器子系统的存储器件生成一个或多个读取命令。 读取命令可以包括地址位置信息。 存储器件包括具有可与地址位置信息寻址的存储器位置的存储器阵列。 存储器位置具有相关联的数据和内部校验位，其中校验位由存储器内部产生用于纠错。 如果存储器设备被配置为检查位读取模式，则响应于读取命令，它发送与所识别的地址位置相关联的内部校验位。 如果存储器件未配置检查位读取模式，则它将响应于读取命令返回数据，而不暴露内部校验位。

公开(公告)号：US09542123B2

公开(公告)日：2017-01-10

申请号：US14952324

申请日：2015-11-25

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Kuljit S. Bains

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/068 ,  G06F11/2094 ,  G06F2201/805 ,  G11C7/1045 ,  G11C7/24 ,  G11C29/025 ,  G11C29/46 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/76 ,  G11C29/83

Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

Abstract translation: 在一个实施例中，存储器设备可以包含设备处理逻辑和模式寄存器。 模式寄存器可以是可以指定存储器件的操作模式的寄存器。 模式寄存器中的字段可以保存可以指示与存储器设备相关联的命令是否被禁用的值。 该值可以保持在现场，直到存储器件被上电或复位为止。 设备处理逻辑可以获取命令的实例。 设备处理逻辑可以基于模式寄存器保持的值来确定该命令是否被禁用。 如果设备处理逻辑确定该命令被禁用，则设备处理逻辑可能不执行该命令的实例。 如果设备处理逻辑确定命令未被禁止，则设备处理逻辑可以执行该命令的实例。

公开(公告)号：US20160350002A1

公开(公告)日：2016-12-01

申请号：US14998058

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： George Vergis ,  Kuljit S. Bains ,  James A. McCall ,  Murugasamy K. Nachimuthu ,  Mohan J. Kumar

IPC: G06F3/06

CPC classification number: G06F12/02 ,  G11C5/04 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

Abstract: A system enables memory device specific self-refresh entry and exit commands. When memory devices on a shared control bus (such as all memory devices in a rank) are in self-refresh, a memory controller can issue a device specific command with a self-refresh exit command and a unique memory device identifier to the memory device. The controller sends the command over the shared control bus, and only the selected, identified memory device will exit self-refresh while the other devices will ignore the command and remain in self-refresh. The controller can then execute data access over a shared data bus with the specific memory device while the other memory devices are in self-refresh.

Abstract translation: 系统启用存储设备特定的自刷新进入和退出命令。 当共享控制总线（诸如等级上的所有存储设备）中的存储设备进行自刷新时，存储器控制器可以向存储器设备发出具有自刷新退出命令和唯一存储器设备标识符的特定于设备的命令 。 控制器通过共享控制总线发送命令，只有选定的已识别的存储设备将退出自刷新，而其他设备将忽略该命令并保持自刷新。 然后，控制器可以通过共享数据总线与特定存储器设备执行数据访问，而其他存储器件处于自刷新状态。

公开(公告)号：US20160254044A1

公开(公告)日：2016-09-01

申请号：US14865754

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert ,  Nadav Bonen ,  Tomer Levy

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4087

Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

Abstract translation: 存储器子系统刷新管理使得命令能够使用单个命令访问跨不同银行组的一个或多个识别的银行。 每个银行组分别单独发送在单独的银行组中发送标识银行或银行的命令，该命令可以导致存储设备访问不同银行组中的银行。 该命令可以是刷新命令。 该命令可以是预充电命令。

公开(公告)号：US09396785B2

公开(公告)日：2016-07-19

申请号：US14271124

申请日：2014-05-06

Applicant: Intel Corporation

Inventor： Kuljit S. Bains

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G06F12/023 ,  G06F2212/1016 ,  G11C11/40611 ,  G11C11/40618 ,  G11C2211/4061

Abstract: On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate. In response to the condition, the refresh rate is dynamically switched. The switching does not require a change of a mode register. Thus, a refresh rate for the memory device can be dynamically changed on the fly.

Abstract translation: 提供从一个存储设备刷新率到另一个的飞行切换。 与存储器件相关联的控制逻辑检测从当前施加的刷新率切换到不同的刷新率的条件。 响应该条件，动态切换刷新率。 切换不需要更改模式寄存器。 因此，可以动态地改变存储器件的刷新率。

公开(公告)号：US20160065212A1

公开(公告)日：2016-03-03

申请号：US14838373

申请日：2015-08-28

Applicant: Intel Corporation

Inventor： James A. McCall ,  Kuljit S. Bains

IPC: H03K19/00 ,  G11C7/10

CPC classification number: H03K19/0005 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4074 ,  G11C11/4093

Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.

Abstract translation: 这里描述了一种用于响应于终止信号电平在存储器的存储器输入 - 输出（I / O）接口之间动态切换一个或多个有限终端阻抗值设置的方法和装置。 该方法包括：为存储器的输入输出（I / O）接口的终端单元设置第一终端阻抗值设置; 当所述存储器未被访问时，将所述第一终端阻抗值设置分配给所述终端单元; 以及响应于终止信号电平从第一终端阻抗值设置切换到第二终端阻抗值设置。

公开(公告)号：US09213491B2

公开(公告)日：2015-12-15

申请号：US14230338

申请日：2014-03-31

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Kuljit S. Bains

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/068 ,  G06F11/2094 ,  G06F2201/805 ,  G11C7/1045 ,  G11C7/24 ,  G11C29/025 ,  G11C29/46 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/76 ,  G11C29/83

Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

Abstract translation: 在一个实施例中，存储器设备可以包含设备处理逻辑和模式寄存器。 模式寄存器可以是可以指定存储器件的操作模式的寄存器。 模式寄存器中的字段可以保存可以指示与存储器设备相关联的命令是否被禁用的值。 该值可以保持在现场，直到存储器件被上电或复位为止。 设备处理逻辑可以获取命令的实例。 设备处理逻辑可以基于模式寄存器保持的值来确定该命令是否被禁用。 如果设备处理逻辑确定该命令被禁用，则设备处理逻辑可能不执行该命令的实例。 如果设备处理逻辑确定命令未被禁止，则设备处理逻辑可以执行该命令的实例。