公开(公告)号：US20150249045A1

公开(公告)日：2015-09-03

申请号：US14194502

申请日：2014-02-28

申请人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

发明人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

IPC分类号： H01L23/495 ,  H01L23/29 ,  H01L21/78

CPC分类号： H01L23/49551 ,  H01L21/561 ,  H01L21/78 ,  H01L23/043 ,  H01L23/24 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/73253

摘要： A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units.

摘要翻译： 一种功率半导体器件的制备方法，包括：提供包含多个芯片安装单元的引线框架，每个芯片安装单元的模板的一个侧边缘向上弯曲并向上延伸，并且一个引线连接到所述芯片安装单元的弯曲侧边缘 模具桨，并且在与模桨相反的方向上延伸; 将半导体芯片附接到所述管芯焊盘的顶表面; 在半导体芯片的前面的每个电极上形成金属凸块，每个金属凸块的顶端从引线的顶表面的平面突出; 加热金属凸块并通过压板压制每个金属凸块的顶端，该压板形成与引线顶表面齐平的平坦顶端表面; 并切割引线框架以分离各个芯片安装单元。

公开(公告)号：US09040356B2

公开(公告)日：2015-05-26

申请号：US12487666

申请日：2009-06-19

申请人： Mike Chang ,  King Owyang ,  Yueh-Se Ho ,  Mohammed Kasem ,  Lixiong Luo ,  Wei-Bing Chu

发明人： Mike Chang ,  King Owyang ,  Yueh-Se Ho ,  Mohammed Kasem ,  Lixiong Luo ,  Wei-Bing Chu

IPC分类号： H01L21/50 ,  H01L23/495 ,  H01L23/31 ,  H01L23/544

CPC分类号： H01L23/49562 ,  H01L23/3107 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.

摘要翻译： 半导体封装包括杯形并保持半导体管芯的引线框架。 引线框架与裸片的一侧上的端子电接触，并且引线框架的引线以这样的方式弯曲，使得引线的一部分与管芯的另一侧共面，其还包含一个或多个端子 。 在引线框架和模具周围形成塑料胶囊。

公开(公告)号：US20140361418A1

公开(公告)日：2014-12-11

申请号：US13913183

申请日：2013-06-07

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

摘要翻译： 本发明涉及倒装芯片的半导体封装以及制造半导体封装的方法。 半导体芯片包括金属氧化物半导体场效应晶体管。 在包括第一基底，第二基底和第三基底的裸片上，在第一基底和第二基底的顶表面上进行半蚀刻或冲孔，以获得多个凹槽，该凹槽将第一基底 进入包括多个第一连接区域的多个区域，并且将第二基座的顶表面分成包括至少第二连接区域的多个区域。 半导体芯片在第一连接区域和第二连接区域处连接到管芯焊盘。

公开(公告)号：US08865523B2

公开(公告)日：2014-10-21

申请号：US13833341

申请日：2013-03-15

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC分类号： H01L23/495 ,  H01L21/78

CPC分类号： H01L23/49562 ,  H01L21/561 ,  H01L21/78 ,  H01L23/06 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49568 ,  H01L2224/32245 ,  H01L2924/13091 ,  H01L2924/00

摘要： A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

摘要翻译： 一种制造半导体封装器件的方法包括将引线框架安装在模制半导体芯片的底部，该底部具有覆盖半导体芯片的顶面的第一塑料封装体，用第二塑料封装体封装引线框和半导体芯片 导电接触体的顶表面电连接到半导体芯片的顶表面上的电极，并暴露在组件结构的顶表面上的导电焊盘，以通过导电接触体提供与电极的外部电连接。

公开(公告)号：US08716069B2

公开(公告)日：2014-05-06

申请号：US13631471

申请日：2012-09-28

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

IPC分类号： H01L21/00 ,  H01R43/00 ,  H01L23/495 ,  H05K5/02

CPC分类号： H01L23/49861 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/49579 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  Y10T29/49121 ,  Y10T29/49172 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

摘要翻译： 半导体器件包括具有覆盖铝合金引线框架的暴露部分的钝化层的铝合金引线框架。 由于铝合金是低成本材料，其硬度和柔韧性适用于冲压，弯曲，成型等变形过程，铝合金引线框架适合批量生产; 此外，由于其重量比铜或铁镍材料低得多，因此铝合金引线框对于半导体器件的生产非常方便。

公开(公告)号：US20130210215A1

公开(公告)日：2013-08-15

申请号：US13396531

申请日：2012-02-14

申请人： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

发明人： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

IPC分类号： H01L21/78

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/94 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00015

摘要： A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a centre area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside.

摘要翻译： 具有背面晶片切割的封装方法包括以下步骤：在晶片的前表面形成支撑结构，然后在晶片背面研磨之后在晶片背面的中心区域沉积金属层以减小晶片厚度; 从形成在金属层的边缘与晶片边缘之间的区域中的前表面的划线的背面检测，并从晶片背面沿着直线形成的直线切割晶片和金属层， 延伸从晶片背面检测的划线部分。

公开(公告)号：US20130134502A1

公开(公告)日：2013-05-30

申请号：US13750944

申请日：2013-01-25

申请人： Yueh-Se Ho ,  Yan Xun Xue

发明人： Yueh-Se Ho ,  Yan Xun Xue

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L23/485 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/03 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

摘要翻译： 描述半导体器件，制造半导体器件的方法和电路封装组件。 半导体器件可以具有带有第一和第二表面的半导体衬底和它们之间的侧壁。 第一和第二表面上的第一和第二导电焊盘与衬底中对应的第一和第二半导体器件结构电接触。 第一表面和侧壁上的绝缘体层覆盖第一表面上的第一导电焊盘的一部分。 在第一导电焊盘和侧壁上的绝缘体层的一部分上的导电层与第二导电焊盘电接触。 绝缘体层防止导电层在第一和第二导电焊盘之间形成电接触。

公开(公告)号：US20130119393A1

公开(公告)日：2013-05-16

申请号：US13294903

申请日：2011-11-11

申请人： TingGang Zhu ,  Anup Bhalla ,  Ping Huang ,  Yueh-se Ho

发明人： TingGang Zhu ,  Anup Bhalla ,  Ping Huang ,  Yueh-se Ho

IPC分类号： H01L29/20 ,  H01L29/06 ,  H01L21/20

CPC分类号： H01L29/872 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/28581 ,  H01L21/30612 ,  H01L21/31111 ,  H01L21/56 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L25/18 ,  H01L27/0248 ,  H01L27/0814 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/405 ,  H01L29/417 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/861 ,  H01L29/8611 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05016 ,  H01L2224/05567 ,  H01L2224/11616 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.

摘要翻译： 使用绝缘基板形成垂直导电氮化物基肖特基二极管，绝缘基板在二极管器件用晶片级模塑料封装在前侧之后被提起。 晶片级成型复合体在二极管器件的前侧提供结构支撑，以允许绝缘基板被提起，使得可以在作为阴极的二极管器件的背面上形成导电层。 因此实现了基于垂直导电氮化物的肖特基二极管。 在另一个实施例中，用于垂直GaN肖特基二极管的保护电路采用与GaN肖特基二极管并联连接的硅基垂直PN结二极管，以转移反向偏置雪崩电流。

公开(公告)号：US20130029461A1

公开(公告)日：2013-01-31

申请号：US13192385

申请日：2011-07-27

申请人： ANUP BHALLA ,  Madhur Bobde ,  Yongping Ding ,  Xiaotian Zhang ,  Yueh-Se Ho

发明人： ANUP BHALLA ,  Madhur Bobde ,  Yongping Ding ,  Xiaotian Zhang ,  Yueh-Se Ho

IPC分类号： H01L21/331

CPC分类号： H01L29/7395 ,  H01L21/2636 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/66333

摘要： A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

摘要翻译： 用于制造阳极短路场效应绝缘栅双极晶体管（IGBT）的方法包括选择性地形成具有相反导电类型的第一和第二半导体注入区。 可以将第二导电类型的场阻挡层生长到衬底或植入衬底中。 外延层可以在衬底上或场停止层上生长。 在外延层内形成一个或多个绝缘栅双极晶体管（IGBT）元件单元。

公开(公告)号：US08362606B2

公开(公告)日：2013-01-29

申请号：US12846743

申请日：2010-07-29

申请人： Yueh-Se Ho ,  Yan Xun Xue

发明人： Yueh-Se Ho ,  Yan Xun Xue

IPC分类号： H01L23/12 ,  H01L21/00

CPC分类号： H01L23/485 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/03 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

摘要翻译： 描述半导体器件，制造半导体器件的方法和电路封装组件。 半导体器件可以具有带有第一和第二表面的半导体衬底和它们之间的侧壁。 第一和第二表面上的第一和第二导电焊盘与衬底中相应的第一和第二半导体器件结构电接触。 第一表面和侧壁上的绝缘体层覆盖第一表面上的第一导电焊盘的一部分。 在第一导电焊盘和侧壁上的绝缘体层的一部分上的导电层与第二导电焊盘电接触。 绝缘体层防止导电层在第一和第二导电焊盘之间形成电接触。