公开(公告)号：US20090121779A1

公开(公告)日：2009-05-14

申请号：US12350147

申请日：2009-01-07

Applicant: Donald R. Disney

Inventor： Donald R. Disney

IPC: H03K3/01

CPC classification number: H02M1/36 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/7835 ,  H01L29/808 ,  H02M3/33507 ,  H03K17/0822

Abstract: A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage provided at a third terminal of the first transistor is substantially proportional to a voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is less than a pinch-off voltage of the first transistor. The voltage provided at the third terminal of the first transistor is substantially constant and less than the voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is greater than the pinch-off voltage of the first transistor. The circuit also includes a control circuit disposed in the first substrate and coupled to the third terminal of the first transistor. The circuit further includes a second transistor disposed in a second substrate. A first terminal of the second transistor coupled to the external voltage.

Abstract translation: 具有高电压检测装置的控制电路。 在一个实施例中，电路包括设置在具有第一，第二和第三端子的第一基板中的第一晶体管。 第一晶体管的第一端子耦合到外部电压。 当第一晶体管的第一和第二端子之间的电压小于第一晶体管的钳位电压时，设置在第一晶体管的第三端处的电压基本上与第一晶体管的第一和第二端子之间的电压成比例， 第一晶体管。 当第一晶体管的第一端和第二端之间的电压大于夹断电压时，在第一晶体管的第三端处提供的电压基本上恒定且小于第一晶体管的第一和第二端之间的电压 的第一晶体管。 电路还包括设置在第一基板中并耦合到第一晶体管的第三端子的控制电路。 电路还包括设置在第二基板中的第二晶体管。 第二晶体管的第一端子耦合到外部电压。

公开(公告)号：US07491611B2

公开(公告)日：2009-02-17

申请号：US11716057

申请日：2007-03-09

Applicant: Donald R. Disney

Inventor： Donald R. Disney

IPC: H01L21/336 ,  H01L31/119

CPC classification number: H02M1/36 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/7835 ,  H01L29/808 ,  H02M3/33507 ,  H03K17/0822

Abstract: A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage provided at a third terminal of the first transistor is substantially proportional to a voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is less than a pinch-off voltage of the first transistor. The voltage provided at the third terminal of the first transistor is substantially constant and less than the voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is greater than the pinch-off voltage of the first transistor. The circuit also includes a control circuit disposed in the first substrate and coupled to the third terminal of the first transistor. The circuit further includes a second transistor disposed in a second substrate. A first terminal of the second transistor coupled to the external voltage.

Abstract translation: 具有高电压检测装置的控制电路。 在一个实施例中，电路包括设置在具有第一，第二和第三端子的第一基板中的第一晶体管。 第一晶体管的第一端子耦合到外部电压。 当第一晶体管的第一和第二端子之间的电压小于第一晶体管的钳位电压时，设置在第一晶体管的第三端处的电压基本上与第一晶体管的第一和第二端子之间的电压成比例， 第一晶体管。 当第一晶体管的第一端和第二端之间的电压大于夹断电压时，在第一晶体管的第三端处提供的电压基本上恒定且小于第一晶体管的第一和第二端之间的电压 的第一晶体管。 电路还包括设置在第一基板中并耦合到第一晶体管的第三端子的控制电路。 电路还包括设置在第二基板中的第二晶体管。 第二晶体管的第一端子耦合到外部电压。

公开(公告)号：US20080230812A1

公开(公告)日：2008-09-25

申请号：US12072611

申请日：2008-02-27

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L29/80

CPC classification number: H01L21/76243 ,  H01L21/26586 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/098 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/086 ,  H01L29/10 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/732 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7835 ,  H01L29/808 ,  H01L29/8613 ,  H01L29/866

Abstract: Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.

Abstract translation: 各种集成电路器件，特别是结型场效应晶体管（JFET）形成在隔离结构内部，该隔离结构包括底板隔离区域和从衬底表面延伸到地板隔离区域的沟槽。 沟槽可以填充有介电材料，或者可以在中间部分具有导电材料，其中介电层衬在沟槽的壁上。 描述了通过使用保护环将基底隔离区域延伸超过沟槽并形成漂移区域来终止隔离结构的各种技术。

公开(公告)号：US20080217729A1

公开(公告)日：2008-09-11

申请号：US12070035

申请日：2008-02-14

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L29/00

CPC classification number: H01L21/76243 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/82285 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0825 ,  H01L27/0826 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/732

Abstract: An isolated CMOS pair of transistors formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract translation: 形成在P型半导体衬底中的隔离的CMOS对晶体管包括N型浸没层隔离区和从衬底表面向底部隔离区向下延伸的填充沟槽。 底部隔离区域和填充沟槽一起形成衬底的隔离袋，其在N阱中包含P沟道MOSFET，在P阱中包含N沟道MOSFET。 衬底不含有外延层，从而克服了与其制造相关的许多问题。

公开(公告)号：US20080210980A1

公开(公告)日：2008-09-04

申请号：US12069941

申请日：2008-02-14

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L27/092

CPC classification number: H01L21/761 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/82285 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0825 ,  H01L27/0826 ,  H01L29/41708 ,  H01L29/732

Abstract: Isolated CMOS transistors formed in a P-type semiconductor substrate include an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract translation: 形成在P型半导体衬底中的隔离CMOS晶体管包括N型浸没式地板隔离区域和从衬底表面向底部隔离区域向下延伸的填充沟槽。 底部隔离区域和填充沟槽一起形成衬底的隔离袋，其在N阱中包含P沟道MOSFET，在P阱中包含N沟道MOSFET。 衬底不含有外延层，从而克服了与其制造相关的许多问题。

公开(公告)号：US20080197445A1

公开(公告)日：2008-08-21

申请号：US12072612

申请日：2008-02-27

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L23/58

CPC classification number: H01L29/7835 ,  H01L21/76264 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/41766 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/808 ,  H01L29/8613 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various integrated circuit devices, including a lateral DMOS transistor, a quasi-vertical DMOS transistor, a junction field-effect transistor (JFET), a depletion-mode MOSFET, and a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.

Abstract translation: 包括横向DMOS晶体管，准垂直DMOS晶体管，结型场效应晶体管（JFET），耗尽型MOSFET和二极管的各种集成电路器件形成在隔离结构内，隔离结构包括地板隔离区域 以及从衬底的表面延伸到地板隔离区的沟槽。 沟槽可以填充有介电材料，或者可以在中间部分具有导电材料，其中介电层衬在沟槽的壁上。 描述了通过使用保护环将基底隔离区域延伸超过沟槽并形成漂移区域来终止隔离结构的各种技术。

公开(公告)号：US06207994B1

公开(公告)日：2001-03-27

申请号：US09245030

申请日：1999-02-05

Applicant: Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

Inventor： Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

IPC: H01L2976

CPC classification number: H01L29/7816 ,  H01L21/26 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7832 ,  H01L29/7835

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract translation: 高电压绝缘栅场效应晶体管包括具有源极和漏极的绝缘栅场效应器件结构，漏极形成有一个延伸的阱区，其具有夹在其中的一个或多个相反导电类型的掩埋层。 一个或多个掩埋层在阱区域的延伸部分中产生相关联的多个并联JFET传导通道。 并联JFET导通通道为HVFET提供低导通状态电阻。

公开(公告)号：US09059329B2

公开(公告)日：2015-06-16

申请号：US13215116

申请日：2011-08-22

Applicant: Donald R. Disney

Inventor： Donald R. Disney

IPC: H01L27/06 ,  H01L29/872 ,  H01L27/07 ,  H01L29/808

CPC classification number: H01L29/8725 ,  H01L27/0727 ,  H01L29/808 ,  H01L29/872

Abstract: The present invention discloses a power device with integrated power transistor and Schottky diode and a method for making the same. The power device comprises a power transistor having a drain region, a Schottky diode in the drain region of the power transistor, and a trench-barrier near the Schottky diode. The trench-barrier is provided to reduce a reverse leakage current of the Schottky diode and minimizes the possibility of introducing undesired parasitic bipolar junction transistor in the power device.

Abstract translation: 本发明公开了一种具有集成功率晶体管和肖特基二极管的功率器件及其制造方法。 功率器件包括功率晶体管，其功率晶体管具有漏极区，功率晶体管的漏极区中的肖特基二极管和肖特基二极管附近的沟槽势垒。 提供沟槽屏障以减少肖特基二极管的反向泄漏电流并且最小化在功率器件中引入不期望的寄生双极结型晶体管的可能性。

公开(公告)号：US08829574B2

公开(公告)日：2014-09-09

申请号：US13334514

申请日：2011-12-22

Applicant: Donald R. Disney ,  Isik C. Kizilyalli ,  Hui Nie ,  Linda Romano ,  Richard J. Brown ,  Madhan Raj

Inventor： Donald R. Disney ,  Isik C. Kizilyalli ,  Hui Nie ,  Linda Romano ,  Richard J. Brown ,  Madhan Raj

IPC: H01L29/808 ,  H01L21/335 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66924 ,  H01L21/027 ,  H01L21/283 ,  H01L21/308 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66446 ,  H01L29/66893 ,  H01L29/66909 ,  H01L29/66916 ,  H01L29/7832 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8086

Abstract: A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.

Abstract translation: 半导体器件包括III族氮化物衬底，耦合到III族氮化物衬底并具有台面的第一III族氮化物外延层和耦合到台面的顶表面的第二III族氮化物外延层。 半导体器件还包括耦合到台面的侧表面的III族氮化物栅极结构，以及被配置为在第二III族氮化物外延层和III族氮化物栅极结构之间提供电绝缘的间隔物。

公开(公告)号：US08749015B2

公开(公告)日：2014-06-10

申请号：US13299254

申请日：2011-11-17

Applicant: Donald R. Disney ,  Andrew P. Edwards ,  Hui Nie ,  Richard J. Brown ,  Isik C. Kizilyalli ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

Inventor： Donald R. Disney ,  Andrew P. Edwards ,  Hui Nie ,  Richard J. Brown ,  Isik C. Kizilyalli ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

IPC: H01L29/06

CPC classification number: H01L21/761 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/872

Abstract: A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.

Abstract translation: 一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二 与第一导电类型相反的第二导电类型的GaN外延层。 第二GaN外延层耦合到第一GaN外延层。 该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。 该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。