公开(公告)号：US08892912B2

公开(公告)日：2014-11-18

申请号：US13100110

申请日：2011-05-03

申请人： Yi-Lin Lai ,  Bo-Ming Huang ,  Kuo-Yu Wu

发明人： Yi-Lin Lai ,  Bo-Ming Huang ,  Kuo-Yu Wu

IPC分类号： G06F1/26

CPC分类号： G06F1/263 ,  G06F1/266 ,  G06F1/3212

摘要： An adaptive universal serial bus (USB) charging method and system are disclosed. In a low-power state, a USB device is charged with a non-USB charging mode. The non-USB charging mode is retained when no variation of a data signal coupled to the USB device is detected. When the data signal possesses variation for a first period, it is switched to a third proprietary charging mode.

摘要翻译： 公开了一种自适应通用串行总线（USB）充电方法和系统。 在低功耗状态下，USB设备以非USB充电模式进行充电。 当不检测到耦合到USB设备的数据信号的变化时，保持非USB充电模式。 当数据信号具有第一周期的变化时，它被切换到第三专有充电模式。

公开(公告)号：US08860463B1

公开(公告)日：2014-10-14

申请号：US13951306

申请日：2013-07-25

申请人： Via Technologies, Inc.

发明人： Imran Qureshi

IPC分类号： H03K19/096 ,  H03K19/0175

CPC分类号： H03K3/356104 ,  G06F2207/3872 ,  H03K19/017581

摘要： A fast dynamic register including a data block, a precharge circuit, a transparent latch, and an output logic gate. The precharge circuit precharges first and second precharge nodes and then releases the first precharge node in response to a clock. The data block evaluates data by either pulling the first precharge node low in response to the clock or does not pull it low, in which case the second precharge node is discharged. The transparent latch passes a state of the second precharge node to a store node when transparent, and otherwise latches the store node. The output logic gate drives an output node to a state based on states of the second precharge node and the store node. The transparent latch may be implemented with relatively small devices to reduce size and power consumption to improve efficiency.

摘要翻译： 包括数据块，预充电电路，透明锁存器和输出逻辑门的快速动态寄存器。 预充电电路对第一和第二预充电节点进行预充电，然后响应于时钟释放第一预充电节点。 数据块通过响应于时钟拉低第一预充电节点或者不将其拉低来估计数据，在这种情况下，第二预充电节点被放电。 透明锁存器在透明时将第二预充电节点的状态传递到存储节点，否则锁存存储节点。 输出逻辑门基于第二预充电节点和存储节点的状态将输出节点驱动到状态。 透明锁存器可以用相对较小的装置来实现，以减小尺寸和功率消耗以提高效率。

公开(公告)号：US08849885B2

公开(公告)日：2014-09-30

申请号：US13491260

申请日：2012-06-07

申请人： Clinton Thomas Glover

发明人： Clinton Thomas Glover

IPC分类号： G06F7/499

CPC分类号： G06F9/30036 ,  G06F9/30014 ,  G06F9/30032

摘要： A hardware integer saturation detector that detects both whether packing a 32-bit integer value causes saturation and whether packing each of first and second 16-bit integer values causes saturation, where the first 16-bit integer value is the upper 16 bits of the 32-bit integer value and the second 16-bit integer value is the lower 16 bits of the 32-bit integer value. The detector includes hardware signal logic, configured to generate four signals with information about the integer values. The hardware integer detector also includes saturation logic, configured to gate the four signals to generate a saturation signal. Each bit of the saturation signal indicates whether packing the 32-bit integer value or whether packing one of the first and second 16-bit integer values will cause saturation respectively.

摘要翻译： 检测是否打包32位整数值的硬件整数饱和检测器会导致饱和，以及是否对第一个和第二个16位整数值进行打包导致饱和，其中第一个16位整数值是32位的高16位 位整数值，第二个16位整数值是32位整数值的低16位。 检测器包括硬件信号逻辑，被配置为生成具有关于整数值的信息的四个信号。 硬件整数检测器还包括饱和逻辑，配置为对四个信号进行门控以产生饱和信号。 饱和信号的每个位指示是否打包32位整数值，或者是否打包第一个和第二个16位整数值之一将分别引起饱和。

公开(公告)号：US08843729B2

公开(公告)日：2014-09-23

申请号：US13034839

申请日：2011-02-25

申请人： Terry Parks

发明人： Terry Parks

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3017 ,  G06F9/30145 ,  G06F9/3857 ,  G06F9/3861

摘要： A microprocessor receives first and second program-adjacent macroinstructions of the instruction set architecture of the microprocessor. The first macroinstruction instructs the microprocessor to move a first operand to a first architectural register from a second architectural register. The second macroinstruction instructs the microprocessor to perform an arithmetic/logic operation using the first operand in the second architectural register and a second operand in a third architectural register to generate a result and to load the result back into the first architectural register. An instruction translator simultaneously translates the first and second program-adjacent macroinstructions into a single micro-operation for execution by an execution unit. The single micro-operation instructs the execution unit to perform the arithmetic/logic operation using the first operand in the second architectural register and the second operand in third architectural register to generate the result and to load the result back into the first architectural register.

摘要翻译： 微处理器接收微处理器的指令集架构的第一和第二程序相邻宏指令。 第一宏指令指示微处理器将第一操作数从第二架构寄存器移动到第一架构寄存器。 第二宏指令指示微处理器使用第二架构寄存器中的第一操作数和第三架构寄存器中的第二操作数来执行算术/逻辑运算，以生成结果并将结果加载回第一架构寄存器。 指令转换器同时将第一和第二程序相邻的宏指令转换为单个微操作以供执行单元执行。 单个微操作指示执行单元使用第二架构寄存器中的第一操作数和第三架构寄存器中的第二操作数来执行算术/逻辑运算，以生成结果并将结果加载回第一架构寄存器。

公开(公告)号：US08842983B2

公开(公告)日：2014-09-23

申请号：US12940347

申请日：2010-11-05

申请人： Jinkuan Tang ,  Jiin Lai ,  Hao-Hsuan Chiu

发明人： Jinkuan Tang ,  Jiin Lai ,  Hao-Hsuan Chiu

IPC分类号： H04B10/08 ,  H04B10/03

CPC分类号： H04B10/03

摘要： A data transmission system and method are provided. The data transmission system includes a first link partner and an optical transceiver unit. The first link partner includes a controller. When the first link partner is in an abnormal operation mode, the controller controls the first link partner to exit from the abnormal operation mode. The optical transceiver unit is coupled between the first link partner and a second link partner and performs data transmission between the first link partner and the second link partner. According to the data transmission system and method, one link partner can accurately detect whether another link partner is coupled to the one link partner through an optical transceiver unit. Accordingly, data transmission between the two link partners can be stably performed through the optical transceiver unit.

摘要翻译： 提供了一种数据传输系统和方法。 数据传输系统包括第一链路伙伴和光收发器单元。 第一个链路伙伴包括一个控制器。 当第一链路伙伴处于异常操作模式时，控制器控制第一链路伙伴退出异常操作模式。 光收发器单元耦合在第一链路伙伴和第二链路伙伴之间，并在第一链路伙伴和第二链路伙伴之间执行数据传输。 根据数据传输系统和方法，一个链路伙伴可以准确地检测另一个链路伙伴是否通过光收发器单元耦合到一个链路伙伴。 因此，可以通过光收发器单元稳定地执行两个链路伙伴之间的数据传输。

公开(公告)号：US08816726B1

公开(公告)日：2014-08-26

申请号：US13888622

申请日：2013-05-07

申请人： Via Technologies, Inc.

发明人： Yeong-Sheng Lee

IPC分类号： H03K3/00 ,  H03K17/16

CPC分类号： H03K19/018528 ,  H04L25/0272

摘要： A differential signaling driver includes a current source, a differential signal generator, and a resistor. The current source is connected between an operation voltage and a first node, and supplies a driving current to the first node. The differential signal generator is connected between the first node and a second node. The differential signal generator receives a digital input signal, and generates a pair of differential output signals at a first output node and a second output node according to the digital input signal. The resistor is connected between the second node and a ground voltage. The differential signal generator couples the first output node to the operation voltage and the second output node to the ground voltage or couples the first output node to the ground voltage and the second output node to the operation voltage according to the digital input signal.

摘要翻译： 差分信号驱动器包括电流源，差分信号发生器和电阻器。 电流源连接在工作电压和第一节点之间，并向第一节点提供驱动电流。 差分信号发生器连接在第一节点和第二节点之间。 差分信号发生器接收数字输入信号，并根据数字输入信号在第一输出节点和第二输出节点产生一对差分输出信号。 电阻连接在第二节点和接地电压之间。 差分信号发生器将第一输出节点与操作电压和第二输出节点耦合到地电压，或者根据数字输入信号将第一输出节点接地电压和第二输出节点耦合到工作电压。

公开(公告)号：US20140223157A1

公开(公告)日：2014-08-07

申请号：US14023689

申请日：2013-09-11

申请人： VIA TECHNOLOGIES, INC.

发明人： XinXi LI ,  Xiaolu YANG ,  Wenting WU ,  Ming LI

IPC分类号： G10L15/00 ,  G06F1/26 ,  G06F9/44

CPC分类号： G10L15/00 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3287 ,  G06F9/4401 ,  Y02D10/171

摘要： The invention discloses a computer system having voice-control function. The computer system includes a voice-recognition module, a shared memory, a microcontroller, a power-management module and a central processing unit. The voice-recognition module receives an external voice signal via a microphone and determines whether the external voice signal corresponds to an operation instruction. The shared memory is used for storing shared state information. The microcontroller is used for setting the shared state information according to the operation instruction when the external voice signal corresponds to the operation instruction. The power-management module generates a power-management signal according to the shared state information in the shared memory. When the power-management module transmits the power-management signal, the central processing unit executes a processing operation corresponding to the operation instruction according to the shared state information in the shared memory.

摘要翻译： 本发明公开了一种具有语音控制功能的计算机系统。 计算机系统包括语音识别模块，共享存储器，微控制器，电源管理模块和中央处理单元。 语音识别模块通过麦克风接收外部语音信号，并确定外部语音信号是否对应于操作指令。 共享内存用于存储共享状态信息。 当外部语音信号对应于操作指令时，微控制器用于根据操作指令设置共享状态信息。 电源管理模块根据共享存储器中的共享状态信息生成电源管理信号。 当电源管理模块发送电源管理信号时，中央处理单元根据共享存储器中的共享状态信息执行与操作指令相对应的处理操作。

公开(公告)号：US08796848B2

公开(公告)日：2014-08-05

申请号：US13004242

申请日：2011-01-11

申请人： Wen-Yuan Chang ,  Wei-Cheng Chen ,  Yeh-Chi Hsu

发明人： Wen-Yuan Chang ,  Wei-Cheng Chen ,  Yeh-Chi Hsu

IPC分类号： H01L23/498 ,  H05K3/24 ,  H01L23/00 ,  H05K3/46 ,  H05K3/40 ,  H05K3/28

CPC分类号： H05K3/242 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2203/054 ,  H05K2203/0723 ,  H01L2224/05099

摘要： A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.

摘要翻译： 电路板包括具有彼此相对的顶表面和底表面的基底，至少设置在顶表面上的顶垫，设置在顶表面上并覆盖顶垫的一部分的顶部阻焊层， 以及设置在顶垫上的预凸块。 顶部阻焊层具有暴露顶部焊盘的一部分的第一开口。 预凸块位于第一开口中并且具有从顶部阻焊层突出的突起。 突起的最大宽度小于或等于顶垫的宽度。 还提供了具有电路板的芯片封装结构。

公开(公告)号：US08793803B2

公开(公告)日：2014-07-29

申请号：US12263230

申请日：2008-10-31

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06Q99/00 ,  G06F21/72 ,  G06F21/70

CPC分类号： G06F21/72 ,  G06F12/1408 ,  G06F21/12 ,  G06F21/14 ,  G06F21/554 ,  G06F21/70 ,  G06F21/71 ,  G06F21/73 ,  G06F21/74 ,  G06F21/75 ,  G06F21/82

摘要： An apparatus including a microprocessor, a system memory, and a secure non-volatile memory. The microprocessor is mounted to a motherboard, and executes non-secure application programs and a secure application program. The system memory stores non-secure application programs, and is mounted to the motherboard and coupled to the microprocessor via a system bus. The microprocessor has secure execution mode logic that detects execution of a secure execution mode return event, and that terminates a secure execution mode within the microprocessor, where the secure execution mode exclusively supports execution of the secure application program. The secure non-volatile memory is coupled to the microprocessor via a private bus and stores the secure application program prior to termination of the secure execution mode, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.

摘要翻译： 一种包括微处理器，系统存储器和安全非易失性存储器的装置。 微处理器安装在主板上，执行非安全应用程序和安全应用程序。 系统存储器存储非安全应用程序，并且被安装到主板并通过系统总线耦合到微处理器。 微处理器具有检测执行安全执行模式返回事件的安全执行模式逻辑，并且终止微处理器内的安全执行模式，其中安全执行模式专门支持安全应用程序的执行。 安全非易失性存储器经由专用总线耦合到微处理器，并且在安全执行模式终止之前存储安全应用程序，其中微处理器与安​​全非易失性存储器之间的专用总线上的事务与 系统总线和微处理器内相应的系统总线资源。

公开(公告)号：US20140208149A1

公开(公告)日：2014-07-24

申请号：US13757575

申请日：2013-02-01

申请人： VIA Technologies, Inc.

发明人： Vanessa S. Canac ,  James R. Lundberg

IPC分类号： G06F1/12

CPC分类号： G11C7/1072 ,  G06F1/12 ,  G06F13/3625 ,  G06F13/4068 ,  G06F13/4217 ,  G06F13/4243 ,  G11C8/18

摘要： An apparatus including a synchronous lag receiver that receives one of a plurality of radially distributed strobes and a data bit, and that delays registering of the data bit by a propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters generates successively delayed versions of the data bit. The first mux receives a value on a lag bus that indicates the propagation time, and selects one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver receives the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and registers the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of distributed strobe signals.

摘要翻译： 一种装置，包括接收多个径向分布的选通中的一个和数据位的同步延迟接收器，并且延迟数据位的登记传播时间。 同步延迟接收器具有第一多个匹配的反相器，第一复用器和位接收器。 第一多个匹配的逆变器产生数据位的连续延迟版本。 第一复用器在延迟总线上接收指示传播时间的值，并且选择与该值对应的数据位的连续延迟版本中的一个。 位接收器接收数据位的连续延迟版本中的一个和多个径向分布的选通信号中的一个，并且在断言多个数据位之后登记数据位的连续延迟版本中的一个的状态 的分布式选通信号。