公开(公告)号：US20130049010A1

公开(公告)日：2013-02-28

申请号：US13641003

申请日：2011-04-13

Applicant: John Roberts ,  Ahmad Mizan ,  Girvan Patterson ,  Greg Klowak

Inventor： John Roberts ,  Ahmad Mizan ,  Girvan Patterson ,  Greg Klowak

IPC: H01L29/20

CPC classification number: H01L29/42316 ,  H01L24/05 ,  H01L24/13 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/085 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/7786 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A Gallium Nitride (GaN) series of devices—transistors and diodes are disclosed—that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional inter-digitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.

Abstract translation: 公开了一种氮化镓（GaN）系列晶体管和二极管，其具有比先前描述的GaN器件具有非常优异的每单位面积的电流处理能力。 改进是由于布局拓扑的改进。 这些器件还包括一个更简单和更好的倒装芯片连接方案和降低热阻的手段。 公开了简化的制造工艺，并且示出了使用岛电极而不是手指电极的布局方案，以增加有效面积密度是常规数字化结构的两到五倍。 可以使用岛拓扑构建超低导通电阻晶体管和非常低的损耗二极管。 具体地，本公开提供了增强所有横向GaN结构的成本/有效性能的手段。

公开(公告)号：US20240393374A1

公开(公告)日：2024-11-28

申请号：US18322441

申请日：2023-05-23

Applicant: GAN SYSTEMS INC.

Inventor： Lucas Andrew MILNER ,  Marco A. ZUNIGA ,  Nan XING ,  Robert Wayne MOUNGER ,  Edward MACROBBIE ,  Sridhar RAMASWAMY ,  Ahmad MIZANNOJEHDEHI ,  Thomas William MACELWEE

IPC: G01R19/00

Abstract: A current sense circuit that allows for accurate sensing of a power current that flows through a power transistor as the power transistor ages. The circuit includes the power transistor, a sense transistor and a pull-up component. The control nodes of the power transistor and the sense transistor are connected, causing the power transistor and sense transistor to be on or off simultaneously. The pull-up component is connected between the input node of the power transistor and the input node of the sense transistor. When power is provided to the pull-up component, and when each of the power transistor and sense transistor are off, the pull-up component forces a voltage present at the sense transistor input node to be approximately equal to a voltage present at the power transistor input node, causing the sense and power transistors to age together.

公开(公告)号：US12027449B2

公开(公告)日：2024-07-02

申请号：US17974794

申请日：2022-10-27

Applicant: GaN Systems Inc.

Inventor： Hossein Mousavian ,  Edward Macrobbie

IPC: H01L29/417 ,  H01L23/482 ,  H01L29/20 ,  H01L29/778 ,  H01L29/861

CPC classification number: H01L23/4824 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786 ,  H01L29/8611

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

公开(公告)号：US11909384B2

公开(公告)日：2024-02-20

申请号：US17741813

申请日：2022-05-11

Applicant: GaN Systems Inc.

Inventor： Di Chen

IPC: H02H3/24 ,  H03K17/08 ,  H03K17/22 ,  H02M1/36 ,  H03K17/687 ,  H03K17/0814

CPC classification number: H03K17/223 ,  H02H3/243 ,  H02M1/36 ,  H03K17/08142 ,  H03K17/687

Abstract: A protected direct-drive depletion-mode (D-mode) GaN semiconductor half-bridge power module is disclosed. Applications include high power inverter applications, such as 100 kW to 200 kW electric vehicle traction inverters, and other motor drives. The high-side switch is a normally-on D-mode GaN semiconductor power switch Q1 in series with a normally-off LV Si MOSFET power switch M1 and the low-side switch is a normally on D-mode GaN semiconductor power switch Q2. The gates of both Q1 and Q2 are directly driven. M1 in series with Q1 provides a high-side switch which is a normally-off device for start-up and fail-safe protection. M1 may also be used for current sensing and overcurrent protection. For example, a control circuit determines an operational mode of M1 responsive to a UVLO signal and a voltage sense signal indicative of an overcurrent event. Examples of single phase and three-phase half-bridge modules and driver circuits are described.

公开(公告)号：US20230370059A1

公开(公告)日：2023-11-16

申请号：US17741813

申请日：2022-05-11

Applicant: GaN Systems Inc.

Inventor： Di CHEN

IPC: H03K17/22 ,  H02M1/36 ,  H02H3/24 ,  H03K17/0814 ,  H03K17/687

CPC classification number: H03K17/223 ,  H02H3/243 ,  H02M1/36 ,  H03K17/08142 ,  H03K17/687

Abstract: A protected direct-drive depletion-mode (D-mode) GaN semiconductor half-bridge power module is disclosed. Applications include high power inverter applications, such as 100kW to 200kW electric vehicle traction inverters, and other motor drives. The high-side switch is a normally-on D-mode GaN semiconductor power switch Q1 in series with a normally-off LV Si MOSFET power switch M1 and the low-side switch is a normally on D-mode GaN semiconductor power switch Q2. The gates of both Q1 and Q2 are directly driven. M1 in series with Q1 provides a high-side switch which is a normally-off device for start-up and fail-safe protection. M1 may also be used for current sensing and overcurrent protection. For example, a control circuit determines an operational mode of M1 responsive to a UVLO signal and a voltage sense signal indicative of an overcurrent event. Examples of single phase and three-phase half-bridge modules and driver circuits are described.

公开(公告)号：US11736100B2

公开(公告)日：2023-08-22

申请号：US17308423

申请日：2021-05-05

Applicant: GaN Systems Inc.

Inventor： Ruoyu Hou ,  Juncheng Lu ,  Larry Spaziani

IPC: H03K17/0812 ,  H03K17/16

CPC classification number: H03K17/08122 ,  H03K17/163

Abstract: An active gate voltage control circuit for a gate driver of a power semiconductor switching device comprising a power semiconductor transistor, such as a GaN HEMT, provides active gate voltage control comprising current burst mode operation and protection mode operation. The gate-source turn-on voltage Vgs(on) is increased in burst mode operation, to allow for a temporary increase of saturation current. In protection mode operation, a multi-stage turn-off may be implemented, comprising reducing Vgs(on) to implement fast soft turn-off, followed by full turn-off to bring Vgs(on) below threshold voltage, to reduce switching transients such as Vds spikes. Circuits of example embodiments provide for burst mode operation for enhanced saturation current, to increase robustness of enhancement mode GaN power switching devices, e.g. under overcurrent and short circuit conditions, or to provide active gate voltage control which adjusts dynamically to specific operating conditions or events.

公开(公告)号：US11705821B2

公开(公告)日：2023-07-18

申请号：US17881203

申请日：2022-08-04

Applicant: GaN Systems Inc.

Inventor： Xuechao Liu ,  Paul Wiener

IPC: H02M3/335 ,  H02M3/158 ,  H02M1/00 ,  H02M1/42

CPC classification number: H02M3/33576 ,  H02M1/0009 ,  H02M1/4208 ,  H02M3/158

Abstract: An architecture for a multi-port AC/DC Switching Mode Power Supply (SMPS) with Power Factor Correction (PFC) comprises power management control (PMC) for PFC On/Off Control and Smart Power Distribution, and optionally, a boost follower circuit. For example, in a universal AC/DC multi-port USB-C Power Delivery (PD) adapter, PMC enables turn-on and turn-off of PFC dependent on output port operational status and a combined load of active output ports. A microprocessor control unit (MCU) receives operational status, a voltage sense input and a current sense input for each USB port, computes output power for each USB port, and executes a power distribution protocol to turn-on or turn-off PFC dependent on the combined load from each USB port. Available power may be distributed intelligently to one or more ports, dependent on load. In an example embodiment, turning-off PFC for low load and low AC line input increases efficiency by 3% to 5%.

公开(公告)号：US20230075393A1

公开(公告)日：2023-03-09

申请号：US17800316

申请日：2021-02-05

Applicant: GaN Systems Inc.

Inventor： Tiefeng SHI ,  Paul WIENER

IPC: H02J50/12 ,  H02J50/00 ,  H02J50/90 ,  H02J50/80 ,  H02J7/00 ,  H01F27/28

Abstract: Apparatus, systems and methods for load-adaptive 3D wireless charging are disclosed. In a 3D charging system of an example embodiment, features comprise a 3D coil design that provides magnetic field distribution coverage for a 3D charging space, e.g.
hemi-spherical space/volume; a push-pull class EF2 PA with EMI filter and transmitter circuitry that provides constant current to the 3D coil, with current direction, phase and timing control capability to adapt to load conditions; reactance shift detection circuitry comprising a voltage sensor, current sensor and phase detector and hardware for fast, real-time, computation of reactance and comparison to upper and lower limits for load-adaptive reactance tuning and for auto-protection; and a switchable tuning capacitor network arrangement of shunt and series capacitors configured for auto-tuning of input impedance, e.g. in response to a X detection trigger signal, which enables both coarse-tuning and uniform fine-tuning steps over an extended reactance range.

公开(公告)号：US20230050580A1

公开(公告)日：2023-02-16

申请号：US17974794

申请日：2022-10-27

Applicant: GaN Systems Inc.

Inventor： Hossein MOUSAVIAN ,  Edward MACROBBIE

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/861 ,  H01L29/778 ,  H01L29/417

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact to pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

公开(公告)号：US20230050485A1

公开(公告)日：2023-02-16

申请号：US17974880

申请日：2022-10-27

Applicant: GaN Systems Inc.

Inventor： Ahmad MIZAN ,  Edward MACROBBIE

IPC: H01L23/482 ,  H01L29/778 ,  H01L29/20

Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a center of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.