公开(公告)号：US10177079B2

公开(公告)日：2019-01-08

申请号：US13634079

申请日：2011-03-18

申请人： Hideo Nishikubo ,  Shunji Masumori ,  Takuya Harada ,  Tomohiro Ishii ,  Hidemichi Fujiwara

发明人： Hideo Nishikubo ,  Shunji Masumori ,  Takuya Harada ,  Tomohiro Ishii ,  Hidemichi Fujiwara

IPC分类号： H01L21/60 ,  H05K13/04 ,  H01L23/492 ,  H01L21/48 ,  H01L23/00

摘要： A conductive connecting member formed on a bonded face of an electrode terminal of a semiconductor or an electrode terminal of a circuit board, the conductive connecting member comprising a porous body formed in such manner that a conductive paste containing metal fine particles (P) having mean primary particle diameter from 10 to 500 nm and an organic solvent (S), or a conductive paste containing the metal fine particles (P) and an organic dispersion medium (D) comprising the organic solvent (S) and an organic binder (R) is heating-treated so as for the metal fine particles (P) to be bonded, the porous body being formed by bonded metal fine particles (P) having mean primary particle diameter from 10 to 500 nm, a porosity thereof being from 5 to 35 volume %, and mean pore diameter being from 1 to 200 nm.

公开(公告)号：US10163840B2

公开(公告)日：2018-12-25

申请号：US14201031

申请日：2014-03-07

申请人： Micron Technology, Inc.

发明人： Teck Kheng Lee

IPC分类号： H01L23/498 ,  H01L21/60 ,  H01L23/00 ,  H01L21/48 ,  H05K3/32 ,  H05K3/40 ,  H01L23/48 ,  H05K3/06

摘要： A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure.

公开(公告)号：US10141182B1

公开(公告)日：2018-11-27

申请号：US15811298

申请日：2017-11-13

申请人： NXP USA, INC.

发明人： Jaynal A. Molla ,  Lakshminarayan Viswanathan ,  Geoffrey Tucker

IPC分类号： H01L21/02 ,  H01L23/40 ,  H01L21/60

摘要： Microelectronic systems having embedded heat dissipation structures are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the steps or processes of obtaining a substrate having a tunnel formed therethrough, attaching a microelectronic component to a frontside of the substrate at a location covering the tunnel, and producing an embedded heat dissipation structure at least partially within the tunnel after attaching the microelectronic component to the substrate. The step of producing may include application of a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate. The bond layer precursor material may then be subjected to sintering process or otherwise cured to form a thermally-conductive component bond layer in contact with the microelectronic component.

公开(公告)号：US10115579B2

公开(公告)日：2018-10-30

申请号：US15815986

申请日：2017-11-17

申请人： ASM Technology Singapore Pte Ltd

发明人： Chun Ho Fan ,  Teng Hock Kuah

IPC分类号： H01L23/00 ,  H01L21/02 ,  H01L21/60

摘要： During the manufacture of a semiconductor package, a semiconductor wafer including a plurality of bond pads on a surface of the wafer is provided and the surface of the wafer is covered with a dielectric material to form a dielectric layer over the bond pads. Portions of the dielectric layer corresponding to positions of the bond pads are removed to form a plurality of wells, wherein each well is configured to form a through-hole between top and bottom surfaces of the dielectric layer for exposing each bond pad. A conductive material is then deposited into the wells to form a conductive layer between the bond pads and a top surface of the dielectric layer. Thereafter, the semiconductor wafer is singulated to form a plurality of semiconductor packages.

公开(公告)号：US10068929B2

公开(公告)日：2018-09-04

申请号：US15391155

申请日：2016-12-27

申请人： LG DISPLAY CO., LTD.

发明人： Sungjoon Min ,  Chanwoo Lee ,  Seulki Kim

IPC分类号： H01L27/12 ,  H01L23/538 ,  H01L21/50 ,  H01L27/32 ,  H01L51/00 ,  H01L21/60

摘要： A display device can include a substrate including a display area, on which an input image is displayed, and a pad part including a convex portion and a concave portion that are alternately positioned outside the display area and have a height difference between them, and a circuit element attached to the pad part and including a bump inserted into the concave portion of the pad part. The pad part can further include a lower pad electrode electrically connected to a signal line extended from the display area, a first insulating layer disposed on the lower pad electrode in the convex portion, and an upper pad electrode disposed on the first insulating layer, connected to the lower pad electrode through a first contact hole penetrating the first insulating layer and extending into at least a portion of the concave portion.

公开(公告)号：US10062582B2

公开(公告)日：2018-08-28

申请号：US14817624

申请日：2015-08-04

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Tsung-Hsien Tsai ,  Chih-Hsien Chiu ,  Hsin-Lung Chung ,  Chien-Cheng Lin

IPC分类号： H01L21/60 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/552 ,  H01L23/00

CPC分类号： H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits.

公开(公告)号：US20180233453A1

公开(公告)日：2018-08-16

申请号：US15951001

申请日：2018-04-11

申请人： Infineon Technologies Americas Corp.

发明人： Eung San Cho ,  Danny Clavette

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L21/52 ,  H01L21/60

CPC分类号： H01L23/5389 ,  H01L21/486 ,  H01L21/52 ,  H01L23/481 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L25/16 ,  H01L2021/6009 ,  H01L2021/60135 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091

摘要： Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed within the chip-embedded substrate, temperature-cycling the chip-embedded substrate to induce solder reflow and define an input/output pin for each one of the at least two contacts, and machining the input/output pin for each one of the at least two contacts to extend exposed from the chip-embedded substrate to a common height within specification tolerance. Such a technique represents a paradigm shift in that the manufacturer of the chip-embedded substrate, as opposed to the immediate customer of the manufacturer, may assume the burden of quality control with respect to minimizing unintended solder void trapping under the input/output pins, thereby reinforcing existing customer loyalty and potentially attracting new customers.

公开(公告)号：US20180211895A1

公开(公告)日：2018-07-26

申请号：US15923412

申请日：2018-03-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： TIEN-CHUNG YANG ,  LIN-CHIH HUANG ,  HSIEN-WEI CHEN ,  AN-JHIH SU ,  LI-HSIEN HUANG

IPC分类号： H01L23/31 ,  H01L23/482 ,  H01L23/485 ,  H01L23/00 ,  H01L21/56 ,  H01L21/60

CPC分类号： H01L23/3114 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L24/94 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2224/0391 ,  H01L2224/04105 ,  H01L2224/10126 ,  H01L2224/11013 ,  H01L2224/11466 ,  H01L2224/11602 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13026 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2224/03

摘要： A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductor over the conductive pad, a polymeric material over the semiconductor substrate and surrounding the conductor, and a seed layer between the polymeric material and the conductor. A top surface of the conductor, a top surface of the polymeric material and a top surface of the seed layer are substantially coplanar.

公开(公告)号：US20180204740A1

公开(公告)日：2018-07-19

申请号：US15919569

申请日：2018-03-13

申请人： Amkor Technology, Inc.

发明人： Tae Ho Yoon ,  Yang Gyoo Jung ,  Min Ho Kim ,  Youn Seok Song ,  Dong Soo Ryu ,  Choong Hoe Kim

IPC分类号： H01L21/48 ,  H01L21/60

CPC分类号： H01L21/4853 ,  G02B27/0927 ,  H01L23/3128 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2021/60112 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/75263 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511

摘要： A system and method for laser assisted bonding of semiconductor die. As non-limiting examples, various aspects of this disclosure provide systems and methods that enhance or control laser irradiation of a semiconductor die, for example spatially and/or temporally, to improve bonding of the semiconductor die to a substrate.

公开(公告)号：US09929069B2

公开(公告)日：2018-03-27

申请号：US15380499

申请日：2016-12-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Tien-Chung Yang ,  Lin-Chih Huang ,  Hsien-Wei Chen ,  An-Jhih Su ,  Li-Hsien Huang

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L23/482 ,  H01L23/485 ,  H01L23/00 ,  H01L21/56 ,  H01L21/60

CPC分类号： H01L23/3114 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L24/94 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2224/0391 ,  H01L2224/04105 ,  H01L2224/10126 ,  H01L2224/11013 ,  H01L2224/11466 ,  H01L2224/11602 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13026 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2224/03

摘要： A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a conductive pad disposed thereon; disposing a polymeric material over the semiconductor substrate and the conductive pad; patterning the polymeric material to form an opening exposing at least a portion of the conductive pad; disposing a conductive layer over the polymeric material and the portion of the conductive pad; and forming a conductor over the portion of the conductive pad and within the opening.