公开(公告)号：US09202756B1

公开(公告)日：2015-12-01

申请号：US14805415

申请日：2015-07-21

Applicant: INOSO, LLC

Inventor： Ziep Tran ,  Kiyoshi Mori ,  Giang Trung Dao ,  Michael Edward Ramon

IPC: H01L21/82 ,  H01L21/86

CPC classification number: H01L21/8213 ,  H01L21/8221 ,  H01L21/845 ,  H01L21/86 ,  H01L27/0211 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1211

Abstract: A method of forming a stacked low temperature transistor and related devices. At least some of the illustrative embodiments are methods comprising forming at least one integrated circuit device on a front surface of a bulk semiconductor substrate, and depositing an inter-layer dielectric on the at least one integrated circuit device. A semiconductor layer may then be deposited on the inter-layer dielectric. In some embodiments, a transistor is formed within the semiconductor layer. In some examples, the transistor includes a gate structure formed over the semiconductor layer as well as source/drain regions formed within the semiconductor layer disposed adjacent to and on either side of the gate structure. A metal layer may then be deposited over the transistor, after which an annealing process is performed to induce a reaction between the source/drain regions and the metal layer.

Abstract translation: 一种叠层低温晶体管及相关器件的形成方法。 示例性实施例中的至少一些是包括在体半导体衬底的前表面上形成至少一个集成电路器件，以及在所述至少一个集成电路器件上沉积层间电介质的方法。 然后可以在层间电介质上沉积半导体层。 在一些实施例中，在半导体层内形成晶体管。 在一些示例中，晶体管包括形成在半导体层上的栅极结构以及形成在与栅极结构的任一侧相邻设置的半导体层内的源极/漏极区域。 然后可以在晶体管上沉积金属层，之后执行退火处理以引起源极/漏极区域与金属层之间的反应。

公开(公告)号：US08138031B2

公开(公告)日：2012-03-20

申请号：US12585554

申请日：2009-09-17

Applicant: Atsushi Yagishita

Inventor： Atsushi Yagishita

IPC: H01L21/86

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of Fins including a semiconductor material on an insulation layer; forming gate insulation films on sidewalls of the Fins; forming a gate electrode which extends in a direction of arrangement of the Fins and which is electrically insulated from the Fins, the gate electrode is common in the Fins on the gate insulation film; implanting an impurity into portions of the Fins by using the gate electrode as a mask to form a source-drain diffusion layer, the portions of the Fins extending on both sides of the gate electrodes; and depositing a conductive material on both sides of the Fins to connect the Fins to each other.

Abstract translation: 制造半导体器件的方法包括在绝缘层上形成包括半导体材料的多个金属丝; 在金属丝的侧壁上形成栅极绝缘膜; 形成栅极电极，所述栅电极在所述鳍片的布置方向上延伸并且与所述鳍状物电绝缘，所述栅极电极在所述栅极绝缘膜上的所述鳍片中是共同的; 通过使用栅极电极作为掩模将杂质注入到薄片的部分中以形成源极 - 漏极扩散层，鳍状物的部分在栅电极的两侧延伸; 以及在所述金属丝的两侧上沉积导电材料以将所述金属丝彼此连接。

公开(公告)号：US20120007054A1

公开(公告)日：2012-01-12

申请号：US12832224

申请日：2010-07-08

Applicant: Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/12 ,  H01L29/24 ,  H01L21/86 ,  H01L21/04

CPC classification number: H01L29/1606 ,  B82Y10/00 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/66431 ,  H01L29/66742 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/78684 ,  H01L51/0048

Abstract: A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity.

Abstract translation: 一种用于形成半导体器件的方法包括在基片上形成碳材料，在碳材料上形成栅叠层，去除基片的一部分以形成由碳材料和基片的一部分限定的至少一个空腔，以及 在所述至少一个空腔中形成导电接触。

公开(公告)号：US20110291193A1

公开(公告)日：2011-12-01

申请号：US12788362

申请日：2010-05-27

Applicant: Andres Bryant ,  Josephine B. Chang ,  Jeffrey W. Sleight

Inventor： Andres Bryant ,  Josephine B. Chang ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L21/86

CPC classification number: H01L27/1203 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

Abstract: A high density, asymmetric, butted junction CMOS inverter, formed on an SOI substrate, may include: an asymmetric p-FET that includes a halo implant on only a source side of the p-FET; an asymmetric n-FET that includes a halo implant on only a source side of the n-FET; and a butted junction comprising an area of said SOI substrate where a drain region of the asymmetric n-FET and a drain region of the asymmetric p-FET are in direct physical contact. Asymmetric halo implants may be formed by a sequential process of covering a first FET of the CMOS inverter with an ion-absorbing structure and applying angled ion radiation to only the source side of the second FET, removing the ion-absorbing structure, covering the first FET with a second ion-absorbing structure, and applying angled ion radiation to only the source side of the second FET. A layout display of CMOS integrated circuit may require one ground rule for the high density, asymmetric butted junction CMOS inverter and another ground rule for other CMOS circuits.

Abstract translation: 形成在SOI衬底上的高密度，不对称对接结CMOS反相器可以包括：非对称p-FET，其仅在p-FET的源极侧包括卤素注入; 一个不对称的n-FET，其仅在n-FET的源极侧包括一个卤素注入; 以及包括所述SOI衬底的区域的对接结，其中所述非对称n-FET的漏极区域和所述非对称p-FET的漏极区域直接物理接触。 可以通过以离子吸收结构覆盖CMOS反相器的第一FET的顺序过程形成非对称晕环植入物，并且仅向第二FET的源极侧施加成角度的离子辐射，去除离子吸收结构，覆盖第一 FET，具有第二离子吸收结构，并且仅向第二FET的源极侧施加成角度的离子辐射。 CMOS集成电路的布局显示可能需要高密度，不对称对接结CMOS反相器和其他CMOS电路的另一个接地规则的一个接地规则。

公开(公告)号：US20100065885A1

公开(公告)日：2010-03-18

申请号：US11813018

申请日：2005-12-15

Applicant: Adrianus W. Ludikhuize

Inventor： Adrianus W. Ludikhuize

IPC: H01L27/12 ,  H01L21/86

CPC classification number: H01L29/402 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7317

Abstract: A semiconductor on insulator device has an insulator layer, an active layer (40) on the insulator layer, a lateral arrangement of collector (10), emitter (30) and base (20) on the active layer, and a high Base-dose region (70) extending under the emitter towards the insulator to suppress vertical current flowing under the emitter. This region (70) reduces the dependence of current-gain and other properties on the substrate (Handle-wafer) voltage. This region can be formed of the same doping type as the base, but having a stronger doping. It can be formed by masked alignment in the same step as an n type layer used as the body for a P-type DMOS transistor.

Abstract translation: 绝缘体上半导体器件具有绝缘体层，绝缘体层上的有源层（40），有源层上的集电极（10），发射极（30）和基极（20）的横向排列，以及高的基剂量 区域（70）在发射极之下延伸到绝缘体以抑制在发射极下方流动的垂直电流。 该区域（70）降低了电流增益和其他性质对衬底（手柄晶片）电压的依赖性。 该区域可以由与基底相同的掺杂类型形成，但具有更强的掺杂。 它可以在与用作P型DMOS晶体管的主体的n型层相同的步骤中通过掩模对准来形成。

公开(公告)号：US20100015764A1

公开(公告)日：2010-01-21

申请号：US12512075

申请日：2009-07-30

Applicant: Hideto Ohnuma ,  Shigeharu Monoe ,  Shunpei Yamazaki

Inventor： Hideto Ohnuma ,  Shigeharu Monoe ,  Shunpei Yamazaki

IPC: H01L21/336 ,  H01L21/86

CPC classification number: H01L27/1214 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/66757 ,  H01L29/78624

Abstract: The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film and has a function of reducing light intensity is employed in a photolithography step of forming a gate electrode, an asymmetrical resist pattern having a region with a thick thickness and a region with a thickness thinner than that of the above region on one side is formed, a gate electrode having a stepped portion is formed, and an LDD region is formed in a self-alignment manner by injecting an impurity element to the semiconductor layer through the region with a thin thickness of the gate electrode.

Abstract translation: 本发明提供一种TFT，其以自对准方式提供至少一个LDD区域，而不形成侧壁间隔物并增加制造步骤的数量。 在形成栅电极的光刻步骤中使用具有由衍射光栅图案或半透射膜形成的辅助图案并具有降低光强度的功能的光掩模或掩模版，具有 形成厚度厚的区域和具有比一面上述区域的厚度薄的区域，形成具有台阶部分的栅电极，并且通过注入杂质以自对准方式形成LDD区域 元件通过具有薄的栅电极厚度的区域到半导体层。

公开(公告)号：US07564100B2

公开(公告)日：2009-07-21

申请号：US11377394

申请日：2006-03-17

Applicant: Kimiaki Shimokawa

Inventor： Kimiaki Shimokawa

IPC: H01L21/86

CPC classification number: H01L21/76251 ,  H01L21/86

Abstract: The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.

Abstract translation: 本发明提供了一种SOS晶片，其包括设置在蓝宝石衬底的背面上的不透明多晶硅层，保护多晶硅层的氮化硅层和抵消在氮化硅层中产生的应力的应力缓和膜，其中 氮化硅层和应力缓和膜设置在背面侧。

公开(公告)号：US20080308897A1

公开(公告)日：2008-12-18

申请号：US12155340

申请日：2008-06-03

Applicant: Tetsuya Kakehata ,  Kazutaka Kuriki

Inventor： Tetsuya Kakehata ,  Kazutaka Kuriki

IPC: H01L21/86 ,  H01L27/12

CPC classification number: H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A substrate with which a semiconductor device with excellent electric characteristics and high reliability can be manufactured is provided. An aspect of the invention is a method for manufacturing a substrate for manufacturing a semiconductor device: a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are stacked in this order over a surface of a semiconductor substrate by a thermal CVD method, and then a weakened layer is formed at a given depth of the semiconductor substrate; the semiconductor substrate and a substrate having an insulating surface are arranged to face each other, and the second silicon oxide film provided for the semiconductor substrate and a supporting substrate are bonded to each other; and the semiconductor substrate is separated at the weakened layer by heat treatment, whereby a semiconductor film separated from the semiconductor substrate is left over the substrate having the insulating surface.

Abstract translation: 提供了可以制造具有优异的电特性和高可靠性的半导体器件的衬底。 本发明的一个方面是一种用于制造半导体器件制造用基板的方法：将第一氧化硅膜，氮化硅膜和第二氧化硅膜依次层叠在半导体基板的表面上， CVD法，然后在半导体衬底的给定深度处形成弱化层; 半导体衬底和具有绝缘表面的衬底被布置成彼此面对，并且设置用于半导体衬底和支撑衬底的第二氧化硅膜彼此接合; 并且通过热处理在弱化层处分离半导体衬底，由此将与半导体衬底分离的半导体膜留在具有绝缘表面的衬底上。

公开(公告)号：US20080044956A1

公开(公告)日：2008-02-21

申请号：US11824739

申请日：2007-07-02

Applicant: Kazushige Takechi

Inventor： Kazushige Takechi

IPC: H01L21/86 ,  C03C15/00 ,  H01L21/00

CPC classification number: H01L29/66007 ,  C03C15/00 ,  C03C17/36 ,  C03C17/3642 ,  C03C17/3644 ,  C03C17/3649 ,  C03C17/38 ,  C03C27/10 ,  H01L21/6708 ,  H01L27/1214 ,  H01L27/1266

Abstract: An apparatus for etching a substrate includes (a) a nozzle system including at least one nozzle through which acid solution containing at least hydrofluoric acid is sprayed onto the substrate, (b) a mover which moves at least one of the nozzle system and the substrate relative to the other in a predetermined direction in such a condition that the substrate and the nozzle system face each other, (c) a filter system which filters off particles out of the acid solution having been sprayed onto the substrate, and (d) a circulation system which circulates the acid solution having been sprayed onto the substrate, to the filter system, and further, to the nozzle system from the filter system.

Abstract translation: 一种用于蚀刻基板的设备包括（a）喷嘴系统，其包括至少一个喷嘴，通过该喷嘴至少含有氢氟酸的酸溶液喷射到基板上，（b）移动喷嘴系统和基板中的至少一个的移动器 （c）过滤系统，该过滤系统将已经喷洒在基材上的酸溶液中的颗粒过滤掉，以及（d）一个 循环系统，其将已经喷洒到基板上的酸溶液循环到过滤器系统，并且进一步从过滤器系统到喷嘴系统。

公开(公告)号：US20080026511A1

公开(公告)日：2008-01-31

申请号：US11820320

申请日：2007-06-19

Applicant: Kei Kanemoto

Inventor： Kei Kanemoto

IPC: H01L21/86

CPC classification number: H01L21/84

Abstract: A method for manufacturing a semiconductor device includes: a) forming a first semiconductor layer which can be etched faster than a semiconductor substrate, on the semiconductor substrate including a first region that is arranged at a predetermined interval and is to be provided with a silicon on insulator (SOI) structure; b) forming a second semiconductor layer etched slower than the first semiconductor layer, on the first semiconductor layer; c) removing the first semiconductor layer and the second semiconductor layer from a second region which is adjacent to the first region via one line and disposed singly to each of the first region, so as to form a recess that exposes the semiconductor substrate, for a support; d) forming a support precursor layer made of insulating material on a region including at least the first region and the second region on the semiconductor substrate; e) etching and removing the support precursor layer except for a part thereof corresponding to the first region and corresponding to a part, including at least the one line, of a bottom part of the recess so as to form a support coupling the recess and the second semiconductor layer; f) etching a part of the first semiconductor layer and the second semiconductor layer by using the support as a mask to expose a first side section of the first semiconductor layer and the second semiconductor layer except for a second side section adjacent to the second region; g) etching and removing the first semiconductor layer selectively to the second semiconductor layer and the semiconductor substrate so as to form a cavity under the second semiconductor layer; h) thermally oxidizing the second semiconductor layer being an upper layer of the cavity and the semiconductor substrate being a lower layer of the cavity so as to form a buried insulating layer composed of a semiconductor oxide film in the cavity; and i) removing the support at least from the first region so as to expose the second semiconductor layer.